【摘要】 <正> 一、引言 验证逻辑设计正确性的传统方法是模拟(Simulation),然而随着数字电路规模和功能扩大,模拟方法已不能保证设计的正确性。与此相对,形式验证(formal verification)方法通过对电路结构的形式进行检查和比较来完成验证。它不需要模拟,因而,避开了模拟信号指数上升的问题。形式验证是一个静态分析,它比动态的逻辑模拟具有更大的潜力。 形式验证的一种方法是将其视为自动定理证明:已知一些公理和已成立的引理,证明某一表达式与另一表达式是等价的。美国Illinois技术研究所的A.S.Wojcik用AURA自动定理证明系统进行了逻辑设计的形式验证,AURA用归结原理作自动定理证明,由于归结法会产生大量子句,因此,证明的效率不是很高。更多还原

【Abstract】 The simulating method is impossible to assert the correctness with the increasing of the size of VLSI circuits, Whereas formal verification based on checking and comparing structures of circuits provides another approach to verify the logic function correctness of a circuit. In this papsr a new formal verification method, term-rewriting technique, is proposed. The basic idea is that two circuits to be verified are converted into Boolean ring expressions, than they are reduced by term-rewriting to the unique simplest Boolean ring expre. ions. This method has been proved useful for the combinational logic circuits.更多还原