【摘要】 本文主要介绍采用较简便的装置及适当的方法,制得几乎无层错、约2μm 厚的薄外延层,从而制造出每门延迟为0.3～0.8n(?) 的高速双极IC.文中还给出用C-V,C-t 法检测外延片的情况.更多还原

【Abstract】 This paper introduces the way to manufac-ture about 2μm thin epitaxial layers that arealmost stacking fault free by means of sim-pler installation and advisable methods.The de-lay time per gate of this high speed bipolarIC is 0.3～0.8ns.The paper also shows the results dedected bythe C-V and C-t methods.更多还原