【摘要】 本文以多元逻辑电路(DYL)中的线性与或门为“细胞,构思了体现这种基本门逻辑结构特长的高速数码乘法器结构方案,获得了比目前国际上商品化的高速乘法器更高的运算速度.实验设计制作的 12位× 12位乘法器实测结果表明:最大乘法时间在10ns左右,并能直接插入TTL电路系统使用. 文中分析了DYL线性与或门在二值逻辑系统中的逻辑结构、电路结构特点,提出了用这种基本门构成高速组合逻辑电路的综合方法,并讨论了实现这种基本门阵列高速的关键.更多还原

【Abstract】 A high speed multiplier has been described by means of Multicell-Type Logic (DYL)Linear AND-OR gate, which reflects the logic speciality of the Linear AND-OR gate.Con-sequently,it achieves much higher speed than the multiplier of international market.The databy measuring a 12bit×12bit multiplier specimen shows: maximal multipling time is about 10as and its usage can be directly inserted in TTL system. The feature of the Linear AND-OR gate about both logic and circuit in binary logic isanalysed.The synthesis for high speed combination logic with this basic gate is presented.The key of achieving high speed of the basic gate array is also discussed.更多还原