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双层多晶硅电极间隙势垒的两维分析

Two Dimensional Analysis of the Potential Barrier under the Gap between Two Electrodes in a Double-Level Polycrystal Silicon Structure

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【作者】 王守武何乃明夏永伟

【Author】 Wang Shouwu/Institute of Semiconductors Academia SinicaHe Naiming/Institute of Semiconductors Academia SinicaXia Yongwei/Institute of Semiconductors Academia Sinica

【机构】 中国科学院半导体研究所中国科学院半导体研究所

【摘要】 通过解两维泊松方程,对有覆盖的双层多晶硅电极MOS结构进行了数值模拟.模拟结果表明,电极覆盖明显降低了双层多晶硅电极间隙的势垒高度.对P型硅衬底,双层多晶硅电极间隙处的势垒高度,随着栅电压的增加先增加,达到一个最大值,然后又下降,在高栅压下趋于一个稳定值.势全高度出现最大值的栅电压,就在相应的无电极间隙的MOS结构的阈电压附近.界面电荷的存在降低了势垒高度,当界面电荷密度大于 1×1011/cm2时,势垒不出现.这种结构的阈电压随电极间隙长度的增加而急剧增加.对间隙长度LGG为0.3μm,栅氧化层厚度Tox为1000A的结构,如果衬底掺杂浓度NA为1×1015/cm3,势垒高度最大值为66meV,在高栅压下仅为30meV.它的阈电压比无电极间隙MOS结构高0.13V.

【Abstract】 A MOS structure with double level polycrystal Silicon electrodes is simulated bysolving two dimensional Poisson equation.The simulated results show that the overlap-ping between two electrodes obviously lowers the potential barrier height under thegap between double level electrodes;the barrir height increases first with the increaseof gate voltage reaching a maximum value and then reduces,tending towards a stablevalue at higher gate voltage.The gate voltage,at which the barrier height has its ma-ximum,just corresponds to the threshold voltage of a MOS structure with zero electro-de gap.The barrier height is reduced by interface state charge and when the interfacestates are greater than 1×1011/cm2,the barrier does not occur.The threshold voltagewith electrode gap increases abruptly as the gap length distance increases.For thestructure with a gap length 0.3μm,a gate dioxide thickness 1000 A and a substrate do-ping density 1×1015/cm3,the maximum barrier height is 66 meV and only 30 meV athigher gate voltages,its threshold voltage is 0.13 V greater than that in the MOS stru-cture with zero gap length.

  • 【文献出处】 半导体学报 ,Chinese Journal of Semiconductors , 编辑部邮箱 ,1985年04期
  • 【下载频次】25
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