【摘要】 本算法根据故障的可检测性导出了电路引线的“G-F”二值描述和“G-F”二值基本运算公式,根据这一公式分别求故障块和敏化块的测试码和敏化条件。为了快速回推(解方程),用故障路标、值区、隐含以及布尔代数运算等措施,效果显著。 由于在时序电路中引入时间参数t和脉冲变量cp,统一了组合电路和时序电路的处理。 本算法已在50万次/秒的计算机上编制了程序,处理了超过4000个门的大型时序电路。故障覆盖率平均达98％,90％的故障定位到一块组件,本文最后给出了几种插件的实测结果。更多还原

【Abstract】 The algorithm given in this paper is a method of test generation of a digital circuit, in which the function block is used as a primitive logic element. The "G-F" two-valued description of the line varisbles and "G-F" two-valued basic calculation formula are derived according to the detectability of faults. In the process of path sensitization, the test of faulty block and sensitized function values of sensitized functional block is generated by the "G-F" two-valued formula respectively. To quicken the backtrace, such strategies as fault flag, implication, value area as well as the Boolean algebraic operation etc. are adopted with remarkable effect. As the time parameter t and clock variable cp are introduced in to the sequential circuits, processing of combinational circuits and sequential circuits becomes unified. The algorithm was programmed on a computer with a speed of 0.5 million times per second. It implemented a test generation of more than 4000 gates of sequential circuits.The mean faulty coverage ratio is up to 98%, and 90% of the faults are located at the right chip. Some real test results of the printed circuits boards are listed at the end of the paper.更多还原