【摘要】 本文从表面栅静电感应晶体管（SIT）的基本物理模型出发,求出了沿沟道中心线的电势分布和沟道势垒高度的解析表达式.根据所得表达式具体计算了一个典型器件在不同栅源电压V_GS和漏源电压V_DS下的电势分布和势垒高度.其结果与1978年J.L.Morenza等人对同一器件用计算机数值分析所得的结果吻合较好. 本文给出了该种器件中势垒存在的物理模型,指出了表面栅与隐埋栅器件在势垒形成上的差别:表面栅器件中势垒的形成与源沟n⁺n结有关;而隐埋栅器件势垒的形成与源沟n⁺n结无关. 本文所得的解析表达式也表明,表面栅结构中势垒的出现需要沟道夹断一定的深度.这与1980年日本J.Ohmi用计算机数值分析所得结论是一致的. 本文所得的势垒高度的解析表达式可以作为进一步求解该种器件各电参数的解析表达式的基础.更多还原

【Abstract】 Starting from the fundamental physical model of the surface-gate SIT, the analysis is made for the operational mechanism of this device,the analytical solution isobtained along the central line of the channel.The distributions about the potentialbarrier is computed at different V_GS and V_DS with the typical device.The result iscompared with the numerical result which had been achieved with the same deviceby J. L.Morenza and D. Esteve in 1978, and it is found that both are consilient. The physical model about the existence of potential barrier in the surface-gateSIT is described and the difference in the forming of potential barrier between the sur-face-gate SIT and buried-gate SIT is explained.The conclusion is made about theexistence of potential barrier.更多还原