【作者】 曹宇；

【导师】 苗澎；

【作者基本信息】 东南大学 ， 电路与系统， 2021， 博士

【摘要】 模数转换器(ADC)作为跨接模拟电路和数字电路的桥梁,被广泛应用于通信、计算机、仪器仪表等领域。经过学术界和工业界几十年的研究,ADC的开发取得了长足的进步,速度和精度不断提高,但是随着摩尔定律的放缓,经典结构的ADC指标不断逼近当前的工艺极限。时间交织ADC采用多个单通道并行工作的方式可以实现系统整体速率的倍增,是突破ADC速度瓶颈的重要方向,但是该架构的性能严重受制于内部多个单通道ADC之间的失配。其中,通道间采样时间失配作为制约时间交织ADC高速性能的主要因素,相对于其他通道间失配,在校正上复杂而困难,且通道间采样时间失配的后台校正方法对于输入信号类型的约束也是限制其应用的重要因素。采样时间失配校正是当前学术研究的热点问题。此外,时间交织ADC的速度和精度受制于其前级高速采样模块带宽和线性度上限,特别是受高速栅压自举开关和输入驱动电路性能的限制。顶层采样系统的指标要求跟随系统相应指标的提高而同步提高,是高性能时间交织ADC模拟域的设计核心,近年来受到学术界越来越多的关注。针对通道间采样时间失配,本文对已有的采样时间失配校正方法做了系统的归纳和总结,在此基础之上提出了一种新型的采样时间失配后台校正方法。该校正方法以参考通道的采样时间为基准,利用输入信号时域采样误差累加比较等相关算法和负反馈逻辑调节时间交织ADC各通道的采样时钟相位。和已有的后台校正方法相比,本文提出的方法可以支持任意类型的模拟输入信号,并且可以拓展到任意通道数。针对高速高精度时间交织ADC指标要求对于系统前端输入驱动电路性能的约束,本文介绍了一款宽带高线性度低功耗驱动电路,其以源跟随器为核心,利用前馈电容和输入自举结构增强驱动电路的线性度。对于4p F的负载电容和单端600m V的输入信号摆幅,差分结构下该驱动电路带宽可以拓展到2.5GHz且增益压缩小于10%。相对于传统源跟随器结构,其线性度可以上升15dB。为了满足系统采样速度的需求,本文提出了一种新型宽带高线性度栅压自举开关。该开关通过电平移位技术减小开关自举结构的导通电阻,加快开关导通速度,从而降低开关的最小导通时间以实现高速采样。在2p F负载电容下,以12bit精度为例,该开关采样速率可以达到5GHz,相比传统结构速度提升了150%。本文采用上述技术设计了一款2GS/s 12bit时间交织ADC,由8路流水线ADC交织形成。系统前端采用了2级分级采样架构。本文提出的前级驱动电路和高速栅压自举开关被用于前级采样系统中。系统顶层嵌入了本文提出的采样时间失配校正方法来校正通道间的采样时间失配。后仿真结果表明,系统在经过采样时间失配校正后SNDR提升了17dB。在第一奈奎斯特域内系统的SNDR超过60dB。为了验证本文提出的通道间采样时间失配校正方法,本论文采用了40nm CMOS集成电路工艺实现了一款625MS/s 12bit 2通道时间交织ADC芯片。测试结果表明,经过校正后,交织系统的SFDR提升了10dB,SNDR提升了7dB,对应ENOB提高了约1.1bit。故系统性能在校正后得到了提升,证明了该校正方法的有效性和实用性。更多还原

【Abstract】 As the bridge between analog circuits and digital circuits,analog to digital converter has been widely used in communication systems,computer science,instruments and many more.After decades of research in academia and industry,the development of ADCs has made significant progress,with their increased speed and accuracy.However,the performance of classical ADC’s structures is approaching the current technological limit for the slowdown of Moore’s law.Time-interleaved ADCs use multiple channels to work in parallel to realize the doubling of the conversion speed of the overall system,which is an important direction to break the speed bottleneck of ADC.However,the performance of this structure is severely constrained by the mismatches between internal sub-ADCs.Among them,the sampling time mismatch between channels is the main factor that restricts the high-speed performance of the time-interleaved ADC.Compared with other mismatches between channels,sampling time mismatch calibration is more complicated and difficult.What’s worse,the back-end calibration algorithm usually imposes constraints on the system input,made itself a hot issue in current academic research.In addition,the upper limits of the bandwidth and linearity of the pre-stage sample-and-hold circuits,especially the performance of the high-speed bootstrapped switches and input buffers,restrict the speed and accuracy of the time-interleaved ADCs.The requirements of these modules increase synchronously with the improvement of the corresponding index of the system,which are critical issues of the analog design in high-performance time-interleaved ADCs and have been more and more concerned by academia in recent years.For sampling time mismatches in the system,this paper summarizes the existing skew correction methods systematically and proposes a new kind of skew background correction method.The proposed method utilizes an extra channel as the sampling time reference and the arithmetic relevant to accumulation and comparison of the sampling error of the input in the time domain.The sampling clock phase of each channel in the time-interleaved ADC is turned in negative feedback logic.Compared with those traditional background skew calibration methods,the proposed method can support any input signals and could be easily extended to any number of interleaved channels.The constraints on the performance of the front-end input driver on account of the requirements of high speed and high precision of time-interleaved ADC,a wideband high-linearity buffer is proposed in low power.This buffer is based on the source follower and its linearity is improved with front-end capacitor and input-bootstrap structure.For the load capacitor of 4pF and the input swing of 600mV in single-ended,the bandwidth of the differential driver could expand to 2.5GHz with the gain compression less than 10%.Compared with typical source followers,the linearity of this design raised 15dB.To meet the sampling rate requirements of the system,a new type of bootstrapped switch presented with high performance.This switch decreases the on-resistance of the bootstrapped loop with level shift structure,which reduces the minimum conduction time of the bootstrapped switch,realized its high-speed applications.With a load capacitor of 2pF,the sampling speed of this bootstrapped switch could achieve 5GHz with its accuracy of 12bit,raised up 150%compared with the typical structure.A 2GS/s 12bit ADC with 8 pipelined ADCs interleaved is designed with the above techniques.The front-end adopts a two-level sub-sampling architecture with the input buffer and high-speed bootstrapped switches proposed used in the fast pre-stage sample-and-hold module.The skew between channels is calibrated with the proposed skew calibration method.The post-simulated results show that the SNDR of the time-interleaved ADC has been improved 17dB after calibration.The SNDR of the system is higher than 60dB with the input in the first Nyquist zone.To verify the proposed sampling time mismatch correction method between channels,a 625MS/s 12bit two-channel time-interleaved ADC is implemented in the 40nm CMOS process.The test results show that the SFDR and SNDR of the interleaved system improved by 17dB and 10dB,respectively,the corresponding ENOB raises by about 1.1bit,proving the practicability and effectiveness of the method.更多还原