【作者】 张力；

【导师】 邹雪城；

【作者基本信息】 华中科技大学 ， 微电子学与固体电子学， 2018， 博士

【摘要】 随着摩尔定律的不断延伸,CMOS(Complementary Metal-Oxide-Semiconductor)工艺器件的尺寸越来越小,集成电路芯片具有了更高的的集成度。但当器件的尺寸来到了深亚微米尺度,进一步缩小的难度越来越大,芯片设计的研究开始朝着三维方向发展,出现了芯片堆叠封装技术。电感耦合互连是一种应用于芯片堆叠封装中的无线互连技术,相对于传统的硅通孔(TSV,Through Silicon Via)互连、Micro-Bump互连等有线互连方式,它有着成本低、兼容性高、灵活性高等优点。但是,电感耦合互连技术也存在着功耗大、电感间会产生串扰、电感占用面积较大等问题,亟待进一步的研究完善。而且由于电感耦合互连出现的时间较短,在有许多场景下的应用需要从头开始设计。本文以电感耦合互连的实际应用为研究对象,对电感耦合的物理模型进行了分析,对电感耦合互连的收发电路,以及相关应用设计所面临的一些实际问题进行了细致探讨。主要内容包含以下几个方面:在片上耦合电感的基础物理特性方面,首先给出了包含串联电感、串联电阻和并联电容的模型,对Greenhouse算法进行了改进,使之可以快速准确的计算片上多层电感的感值。然后由片上电感的模型导出了电感耦合的等效电路模型,得到了电感耦合的传递函数和时/频域特性。在互感的计算上,基于Biot-Savart定律推导出了一个关于电感直径、垂直距离和对准偏移的计算公式,可以快速直观地评估不同尺寸、不同位置下电感间互感的变化。进一步用互感计算的结果,对电感耦合串扰进行计算分析,并设计了实验对其验证。在电路层面上,对电感耦合互连的收发电路进行了低功耗方面的设计。由对传统的NRZ(Non return-to-zero)异步收发电路的分析着手,得到其功耗过大是由于电流恒定的结论。电流脉冲调制可以降低电流信号的占空比,进而降低功耗。在NRZ和BPM(Bi-phase modulation)两种脉冲调制的基础上,提出了UPM(Uni-pulse modulation)调制电路,降低功耗的同时,由于其信号脉冲的单一性,电感间的串扰也得到了有效的减弱。提出了适用于UPM调制的电感级联的工作方式,通过多个电感通道的串联合用一股电流来进一步降低功耗,采用了两种电路来实现,其中V型电路的功耗降低程度较大,而H型电路具有更好的频率特性。在应用方面,对电感耦合互连在多层堆叠芯片中的连续传输方式进行了设计。电感耦合互连的连续传输,要在使用电感数量尽量少的情况下,保证不同层次之间互不干扰,我们为此提出了两种连续传输路径——带屏蔽层的双电感路径和不带屏蔽层的三电感路径,对其工作方式和特点进行了介绍;然后对相应的芯片堆叠结构提出了三种方案。针对多层堆叠的存储器芯片,提出了使用有限状态机的片选方式,可以减少使用芯片Pad和引线的数量,并且介绍了使用电感耦合互连作为存储器接口的时序控制方式,使之与传统存储器控制电路兼容。最后,对采用电感耦合互连的片上网络进行了初步的研究。使用电感耦合互连构造片上网络,最大的优点就是可以利用其封装操作的灵活性,根据需求在网络中添加、删除和替换芯片(节点)。首先提出了构造单向环路网络的方法,然后在它的基础上,利用电感耦合收发器可以改变收发模式的特点,将其扩展成为双向环路网络,可以在一个周期内动态地改变链路的通信方向,从而达到降低延迟的目的。然后,将虚通道流控和气泡流控两种流控机制应用在环路网络上,在延迟、吞吐量、硬件面积开销和应用性能四个方面比较它们的性能。更多还原

【Abstract】 With the continuous extension of Moore’s law,devices in the CMOS(complementary metaloxide-semiconductor)process are becoming smaller and smaller,and the integrated circuits on chip have larger scale.However,when the size of the devices reaches the deep sub-micron scale,it becomes difficult to further reduce.The research of chip design begins to develop in three dimensions,and the technology of chips stacked packaging is emerging.Inductive-coupling interconnect is a kind of wireless interconnection applied to the chips stacked packaging,compared with traditional wire interconnections,such as TSV(Through Silicon Via)interconnection and Micro-Bump interconnection,it has advantages of low cost,high compatibility and high flexibility.However,the inductive-coupling interconnect technology also has problems such as high power consumption,crosstalk between inductors and large area of inductance,which should be further studied and improved.Moreover,due to the short time of inductive-coupling interconnection,applications in many scenarios need to be designed from scratch.With the emphasis on application,the inductive-coupling physical model is analyzed,and also some critical issues about the transceiver circuit and related application design are studied in this dissertation.The main contents are as follows:In terms of the fundamental physical properties of the coupling inductors,the on-chip inductor model is expounded firstly,the basic physical properties are given contains series inductance,series resistance and the shunt capacitance.The Greenhouse algorithm is improved,can make quick and accurate calculation of series inductance of multilayer inductor.Then the equivalent circuit model of inductive-coupling is derived from the inductor model,and the transfer function and time/frequency domain characteristics of inductive-coupling are obtained.A mutual inductance calculate formula is deduced based on Biot-Savart law,can rapid evaluate the mutual inductance change under various inductor sizes and relative positions.Furthermore,the inductivecoupling crosstalk is calculated and analyzed by means of mutual inductance calculation.At the circuit level,the design of low power consumption is carried out on the inductivecoupling transceiver circuit.The traditional NRZ(non-return-to-zero)asynchronous transceiver circuit is introduced,it’s a high power consumption circuit because that its current is constant.The current pulse modulation can reduce the duty ratio of the current wave and reduce the power consumption.Based on the NRZ and BPM(bi-phase modulation),a UPM(uni-phase modulation)circuit is proposed,further reducing power consumption,at the same time,due to the singularity of the signal pulse,crosstalk between inductors also has been effectively reduced.And then puts forward the inductor cascade works,multiple series inductive-coupling channel share one current to reduce the power consumption.Two types of circuit are adopted,the V-type circuit can save more power and the H-type circuit has better frequency characteristics.At the application level,the continuous transmission mode of inductive-coupling interconnection in multi-chip stacking is designed.To realize the continuous transmission of inductive-coupling interconnection,using less inductors and avoiding crosstalk between layers,we proposes two consecutive transmission path-double inductors with shield and three inductors without shield.Then the corresponding stacking structures are introduced.For multilayer stacked memory chips using inductive-coupling interconnection,a FSM(finite state machine)chip select method is proposed,can reduce the amount of chip pad and lead.And then introduces the control mode of the memory interface using inductive-coupling interconnection,which is compatible with traditional memory controller.Finally,a preliminary study of No C(network on chip)with inductive-coupling interconnection is carried out.The most obvious advantage of No C with inductive-coupling interconnection is the flexibility of the package operation to add,remove,and replace chips in the network.First we proposed a method to construct a unidirectional ring network.Because of the inductive-coupling transceiver can alter its mode of transmit or receive,the unidirectional ring network can be transformed to a bidirectional ring network.With changing communicate direction dynamically in one cycle,the latency of network can be reduced.Then,the virtual channel flow control and bubble flow control are applied to the uni-and bi-directional ring network,their performances are compared in terms of latency,throughput,hardware scale and application performance.更多还原