【作者】 刘扬；

【导师】 李智群；

【作者基本信息】 东南大学 ， 电路与系统， 2019， 博士

【摘要】 60GHz通信技术是近年来无线通信领域研究的热点,该技术可广泛应用于无线个域网、影音信号传输、无线USB等短距离高速率数据传输业务。目前,国内外各大标准化组织已提出了各种60GHz通信标准,如ECMA-387、IEEE-802.15.3c、IEEE-802.11aj等,规定了相应的载波频率、信道带宽等关键技术指标。基于以上标准的收发机系统和集成电路设计已经成为相关领域的研究热点。频率综合器作为收发机系统的重要组成部分,其性能直接影响系统的传输速率与误码率。因此,研究和设计应用于60GHz通信系统的频率综合器具有重要理论意义和应用价值。本文基于CMOS工艺,对应用于60GHz通信系统的频率综合器关键技术进行了研究。在研究与分析的基础上,设计了频率综合器中的关键模块电路,包括压控振荡器、分频器、鉴频鉴相器、电荷泵、锁相环和倍频器,并进行了流片与测试验证。本文讨论了锁相环频率综合器的结构及原理,对锁相环的稳定性和频率综合器相位噪声的组成进行了分析。基于60GHz滑动中频收发机系统的需求,提出48GHz频率综合器的系统级设计方案,并建立了频率综合器的行为级模型。基于行为级模型对频率综合器进行相位噪声仿真,并根据仿真结果对锁相环的环路带宽进行优化设计。基于环路带宽的优化结果进行了锁相环的时域仿真,验证了环路锁定功能,确定了环路的锁定时间。根据上述计算与仿真结果确定了频率综合器各模块的关键设计指标。本文讨论了压控振荡器的工作原理和典型结构,并对相位噪声的产生及组成进行分析,研究压控振荡器相位噪声的优化方法。在此基础上,使用互补交叉耦合结构设计了24GHz压控振荡器电路,并进行了元件参数的计算。对振荡器中的谐振元件进行了分析与优化,使用了开关电容阵列以拓展频率调谐范围、降低相位噪声。对压控振荡器电路进行了流片测试,测试结果表明,振荡器的输出频率范围为22.85~26.1GHz,1MHz频率偏移处的相位噪声小于-95.56dBc/Hz,核心电路功耗约为6mW。本文讨论了分频器的工作原理和典型结构,设计了24GHz高速二分频器芯片和12GHz脉冲-吞咽计数器电路,其中,24GHz高速二分频器采用伪差分源极耦合逻辑结构设计。对电路进行了流片测试,测试结果表明,在输入信号功率为0dBm的条件下,高速二分频器的工作频率为4~33GHz,功耗约为3.6mW;脉冲-吞咽计数器的工作频率为8~13GHz,功耗约为7.7mW。本文讨论了鉴频鉴相器和电荷泵的工作原理和典型结构,设计了108MHz高速鉴频鉴相器电路芯片和电荷泵电路芯片。鉴频鉴相器电路使用边沿触发型结构设计。电荷泵电路使用带复制支路的漏极开关结构设计。对电路进行了流片测试,测试结果表明,鉴频鉴相器的鉴相范围为-355~+355°,且无明显死区,电路功耗约为1mW。电荷泵电路在输出电压为0.25~1.05V的范围内具有良好的匹配特性,匹配误差不超过1%。本文讨论了锁相环系统集成技术,包括模块间的信号传递与隔离技术。在此基础上,对压控振荡器、高速二分频器、脉冲吞咽计数器、鉴频鉴相器、电荷泵和环路滤波器电路模块进行了系统集成,设计了24GHz锁相环芯片,并进行了流片测试。测试结果表明,该锁相环的频率锁定范围约为23.3~25.9GHz,输出频率分辨率为216MHz。1MHz频率偏移处的相位噪声约为-95.6~-98.3dBc/Hz,108MHz处的参考频率杂散约为-54.3~-62.5dBc。电路功耗约为45.6mW。本文讨论了二倍频器的设计与优化方法。在分析二倍频器基本原理和典型结构的基础上,创新性地提出了互补推-推结构二倍频器设计和使用负阻的转换增益提升技术。与传统的推-推结构二倍频器相比,互补推-推结构可以直接产生差分输出信号,而无需使用额外的巴伦元件,便于系统集成。使用负阻的转换增益提升技术不仅可以提升倍频器的转换增益,还可以提高最大增益频率。基于上述技术,设计了48GHz二倍频器电路芯片,并进行了流片测试。测试结果表明,该二倍频器电路的输出3-dB带宽为40~54GHz,最大转换增益为-6.1dB,基频抑制比大于29.5dB,电路功耗16mW。更多还原

【Abstract】 In recent years,60 GHz communication technology has become a hot research topic in the field of wireless communication,and this technology could be widely used in wireless personal area network,audio-visual signal transmission,wireless USB and other short-distance high-speed data transmission applications.At present,many major standardization organizations at home and abroad have proposed 60 GHz communication standards,such as ECMA-387,IEEE-802.15.3c,IEEE-802.11 aj,etc.,which specified the corresponding carrier frequency,channel bandwidth and other key parameters.Transceiver system and integrated circuit design based on the above standards are becoming research hotspots in related fields.As an important part of a transceiver system,the performance of frequency synthesizer directly affects the transmission data-rate and BER of the system.Therefore,the research and design of frequency synthesizer applied in 60 GHz communication system is of great theoretical significance and application value.The key technologies of frequency synthesizer applied in 60 GHz communication system using CMOS technology are studied in this paper.Based on research and analysis,the circuits of key modules in frequency synthesizer are designed,including voltage controlled oscillator(VCO),frequency divider,phase and frequency detector(PFD),charge pump(CP),phase-locked loop(PLL)and frequency doubler.The circuits have been taped out and measurement results are proposed.The structure and principle of phase-locked loop frequency synthesizer are discussed in this paper.The stability of PLL and the composition of phase noise of frequency synthesizer are analyzed.Based on the requirement of 60 GHz sliding IF transceiver system,the system-level topology of 48 GHz frequency synthesizer is proposed,and the behavior model of the frequency synthesizer is established.The phase noise of the frequency synthesizer is simulated based on the behavioral level model,and the loop bandwidth of the PLL is optimized according to the simulation results.Based on the optimization results of loop bandwidth,the time domain simulation of PLL is carried out to verify the lock-in function and determine the lock-in time of the loop.According to the calculation and simulation results above,the key parameter of each module of the frequency synthesizer are determined.The principle and typical structure of VCO are discussed in this paper.The generation and composition of phase noise are analyzed,and the optimization method of phase noise is studied.On this basis,a 24 GHz VCO circuit using complementary cross-coupling structure is designed,and the component parameters are calculated.The resonant components in the oscillator are analyzed and optimized.Switched capacitor arrays are used to expand the frequency tuning range and reduce phase noise.The VCO circuit has been taped out.The measurement results shows that,the output frequency of the oscillator ranges from 22.85 to 26.1 GHz,the phase noise at 1 MHz frequency offset is less than-95.56 dBc/Hz,the power consumption of the VCO core is about 6 mW.Principle and typical structure of frequency dividers are discussed in this paper.A 24 GHz high-speed divide-by-2 circuit and a 12 GHz pulse-swallow counter circuit are designed.The high-speed divide-by-2 is designed using pseudo-differential sourcecoupled logic structure.The circuits have been taped out.The measurement results shows that,with an input signal power of 0 dBm,the working frequency of the divideby-2 is 4~33 GHz,and the power consumption is about 3.6 mW,the working frequency of the pulse-swallow counter is 8~13 GHz,and the power consumption is about 7.7 mW.The principle and typical structure of PFD and CP are discussed in this paper.A 108 MHz high speed PFD and a CP circuit are designed.The PFD circuit is designed using edge-triggered structure.The CP circuit is designed using drain-switched structure with duplicated branch.The circuits have been taped out.The measurement results shows that,the phase detection range of the PFD is 355~ +355 degrees,and no obvious dead zone is found.The power consumption of the PFD is about 1mW.Charge pump circuit has good matching characteristics in the output voltage range of 0.25~1.05 V,and the mismatching error is less than 1%.The integration technology of PLL system,including module interconnection and isolation technology,is discussed in this paper.On this basis,a 24 GHz PLL chip is designed and integrated using circuit modules as VCO,divide-by-2,pulse-swallow counter,PFD,CP and loop filter.The chip has been taped out.The measurement results shows that,the frequency locking range of the PLL is about 23.3~25.9 GHz,and frequency step is 216 MHz,the phase noise at 1 MHz frequency offset is about-95.6~-98.3 dBc/Hz,the reference frequency spurious at 108 MHz is about-54.3~-62.5 dBc,the power consumption of the circuit is about 45.6 mW.The design and optimization of frequency doubler is discussed in this paper.Based on analyzation of the principle and typical structure of frequency doubler,a novel complementary push-push structure frequency doubler and a conversion gain enhancing technique using negative resistance are proposed.Compared with the classical push-push structure,the complementary push-push frequency doubler can generate differential output signals directly without additional Balun,which is convenient for system integration.Conversion gain enhancing technology using negative resistance could not only improve the conversion gain of frequency doubler,but also increase the maximum gain frequency.Based on the above technology,a 48 GHz frequency doubler is designed and taped out.The measurement results shows that,the output 3-dB bandwidth of the frequency doubler is 40~54 GHz,the peak conversion gain is-6.1 dB,the minimum fundamental rejection ratio is 29.5 dB,and the power consumption is 16 mW.更多还原