【作者】 王旭；

【导师】 毛志刚；

【作者基本信息】 上海交通大学 ， 芯片设计与系统， 2015， 博士

【摘要】 SRAM是电子系统中不可或缺的重要组成部分,用于数据或指令的临时存储,具有速度快、功耗低、易于嵌入式集成等优点,是CPU中缓存的首选器件。在现代高性能处理器中,SRAM所占芯片的面积已经超过80%。未来几年,随着移动互联网、可穿戴电子设备和物联网的爆发式增长,芯片的功耗将受到更严格的要求和更严峻的挑战,低功耗SRAM设计将变得越来越重要。本文研究了SRAM的低功耗设计方法。在论文研究范围的选择方面,要求所研究的技术或方法要易于实现、可以被广泛应用、对性能不能有过多牺牲。针对这样的研究范围,本文提出了优化的电荷再利用SRAM技术、位线电荷泵SRAM技术和电源电荷泵SRAM技术。本文首先总结了SRAM存储器的特点、分类和发展情况。第二,分析了SRAM的电路结构、优化方法、稳定性评估以及功耗构成。通过对有代表性的传统6T-SRAM仿真,得出位线的动态功耗是整个SRAM中耗电最大的部分这一结论,并进一步分析指出位线写操作的功耗大于读操作的功耗。所以本文的主要研究方向聚焦在写操作时的位线充放电功耗。第三,目前已有的位线电荷再利用技术存在电路复杂、需要引入额外电压源等不足,针对这些不足,本文提出了新的解决方案。此外,针对读操作应用了读出位线分级的策略,为了提高操作的稳定性提出了两种8T-SRAM单元结构,最终降低了功耗又提高了稳定性。第四,针对目前电荷泵SRAM方案中,要将阵列分为两部分且性能不一致、降低电源稳定性、设计复杂、需要引入额外电压源等缺点,本文提出了位线电荷泵SRAM的方案,并在此基础上进一步提出了电源电荷泵SRAM方案。电荷泵SRAM技术的特点是:在写操作时用电荷泵的电容收集位线泄放的电荷,然后再利用电荷泵升压的原理将收集的电荷转移到需要用电的电路中继续使用。第五,针对所有提出的低功耗技术,本文全部完成了版图设计,并通过仿真验证了这些设计的可行性并对结果做了分析和比较。本文的主要工作及结果有:用65nm低功耗工艺库设计了一块64Kb的SRAM,同时应用了本文提出的位线电荷再利用技术、读出位线分级技术和两种不同类型的8管单元结构。仿真结果显示比传统6T-SRAM节省功耗36.9%,而静态噪声容限提高了162%;用180nm数字工艺完成了一块8Kb的位线电荷泵SRAM,比同工艺下6T-SRAM节省11%的功耗,此块SRAM嵌入到一款8051 MCU中正常工作,满足科研课题的需求;用130nm射频工艺完成了一块32Kb的电源电荷泵SRAM版图,仿真结果表明,它比传统6T-SRAM节省16.2%的功耗,同时最高工作频率比位线电荷泵SRAM提高80%。更多还原

【Abstract】 SRAM(Static Random Access Memory)is one of the important components in electronic system.It is applied to store data and instruction temporarily.Because of high-speed,low-power and easy to be integrated,it becomes the primary candidate for cache in CPU.In the modern high performance CPUs,the area of SRAM is over 80%.By the booming market of mobile internet,wearable electronic devices and internet of things,the power consumption of chips will be facing the strict requirement and serious challenge in the next a few years,so the low power design methodology for SRAM is becoming more and more important.The main contribution of this thesis is to explore the low power design methodology for SRAMs,which is focus on schematic level,can be used with the scale-down of technology and will not affect the performance too much.In this thesis,we propose a new charge-recycling SRAM,bit-line charge pump SRAM and voltage supply charge pump SRAM techniques.First,we introduce the principle,classify and development history of SRAMs.Second,we analyze the circuit structure,optimizing mothod and estimation of stability,then analyze the total power consumption of conventional 6T-SRAM,and find out bitline charging and discharging activity is the most significant part among various power consumption components in SRAMs.Furthermore,the bitline power consumption in write cycle is more than that in read cycle.So the key point of the thesis is focus on bitline charging and discharging activity in the write cycle.Thrid,for bitline charging and discharging power consumption,the existing charge-recycling technique can reduce a lot of bitline power consumption,however,there are some shortcomings such as the high complexity and additional circuits are required.In this thesis,we propose a new bit-line charge-recycling solution to improve the inherent drawbacks of existing method.In addition,hierachical bitline scheme is presented in read cycle and two types of 8T-SRAM cells are adopt in the same array.These three improvements reduce the power consumption and enhance the stability.Fourth,the existing charge pump SRAM has some shortcomings,such as different performance for two splitted arrays,decreasing stability,high complexity and requiring additional DC voltage supply,et al.The proposed bit-line charge pump SRAM conquers these shortcomings.Furthermore,another voltage supply charge pump SRAM circuit is proposed.The key point of charge pump SRAM technique is,sharing the bit-line charge in write operation,and then re-using the charge by the function of charge pump.Last,post simulation is applied to prove that all of the proposed techniques can be manufactured and to analyze and compare.A 64 Kb 8T-SRAM layout is completed with 65 nm ultra-low-power technology.The proposed new bitline charge-recycling solution,hierachical read bitline scheme and two types of 8T-SRAM cells are applied in this SRAM design.The power consumption is 36.9% less and Static Noise Margin is 162% more than conventional 6T-SRAM in the same technology.An 8Kb bit-line charge pump SRAM layout is designed with 180 nm CMOS digital technology.11% power cost is saved comparing to conventional 6T-SRAM without charge pump.This proposed bit-line charge pump SRAM is embedded into an 8051 MCU,and the system runs smoothly and fulfills the specification.A 32 Kb voltage supply charge pump SRAM layout is completed with 130 nm RF technology.The simulation result indicates that it reduces 16.2% power consumption compaired with conventional 6T-SRAM and increases 80% highest frequence compaired with bit-line charge pump SRAM in the same technology.更多还原