【作者】 刘伟；

【导师】 魏廷存；

【作者基本信息】 西北工业大学 ， 计算机科学与技术， 2017， 博士

【摘要】 碲锌镉(Cadmium Zinc Telluride,CZT)探测器被公认为是具有广阔发展前景的下一代半导体辐射探测器,基于CZT探测器的成像系统在空间探测、生物医学成像、放射性监测以及安全检查等领域具有广泛的用途。前端读出系统是CZT探测器系统的核心器件,其功能是将CZT探测器输出的微弱电信号进行低噪声放大、整形和数字化。模数转换器(Analog to Digital Converter,ADC)是前端读出系统的重要组成部分,要求具有高分辨率、高转换速率、小面积、低功耗以及抗辐照的特点。本文主要致力于应用在CZT探测器成像系统的逐次逼近(Successive Approximation Register,SAR)ADC的研究与实现,主要研究工作和创新点如下。1、主要研究工作(1)电阻电容混合结构SAR-ADC芯片的研究与设计针对应用于便携式γ谱仪的CZT探测器系统,设计实现了一款12-bit 1 MS/s电阻电容混合结构SAR-ADC芯片,具有电路结构简单、易于实现的特点。该芯片采用6-bit C-DAC和6-bit R-DAC的组合DAC结构,在SAR-ADC的精度和功耗方面取得了良好的折中。另外,6-bit C-DAC采用单位电容阵列实现,提高了SAR-ADC的线性度。测试结果表明,该芯片功耗为10 mW,有源部分面积为1.274 mm~2,无失码现象,有效位为10.94-bit。(2)单位桥电容结构SAR-ADC芯片的研究与设计针对应用于PET生物医学成像的CZT探测器系统,设计实现了一款12-bit 1 MS/s单位桥电容结构SAR-ADC芯片,具有低功耗和小面积的特点。与传统的分数桥电容结构C-DAC相比,采用单位桥电容C-DAC结构提高了桥电容的匹配精度。为了消除周期性的失码现象,提出了随机码校准算法。测试结果表明,该芯片功耗为5 mW,有源部分面积为0.943 mm~2,在校准后无失码现象,有效位为11.00-bit,。(3)亚二进制电容结构SAR-ADC芯片的研究与设计针对应用于空间X/γ-射线探测的CZT探测器系统,设计实现了一款12-bit 1 MS/s斜坡数字逐位校准亚二进制电容结构SAR-ADC芯片,具有低功耗、小面积和抗辐照的特点,适合于多通道集成应用。为了减小电容工艺误差对SAR-ADC的精度影响,提出了斜坡数字逐位校准算法。测试结果表明,该芯片功耗为3 mW,有源部分面积为0.687mm~2,校准后无失码现象,有效位为10.88-bit。以上三款SAR-ADC芯片的研究与设计,均采用TSMC 0.35μm CMOS商用工艺。(4)SAR-ADC芯片的抗辐照加固设计针对应用于空间X/γ-射线探测的CZT探测器系统,为了提高SAR-ADC芯片的抗辐照能力,分别从电路和版图层面进行了抗辐照加固设计。针对总剂量效应(TID)引起CMOS管的阈值电压漂移的问题,在比较器的设计中采用了失调电压自消除技术。针对单粒子翻转(SEU)效应,比较器的锁存器中采用了电阻延时的方法,移位寄存器中采用了双内锁单元(DICE)结构。针对单粒子闩锁(SEL)效应,主要在版图层面进行了加固设计,包括给数字单元库的NMOS与PMOS加保护环,以及加大NMOS与PMOS之间的距离。2、主要创新点(1)提出了一种失调电压自消除高速比较器电路比较器的失调电压严重影响SAR-ADC的变换精度。对于传统的比较器失调电压消除电路,由于失调存储电容串联在信号通路上,降低了比较器的响应速度。本文提出了一种失调电压自消除高速比较器,将失调存储电容转移到输出负载管两端,而在信号通路中未引入任何额外的电容负载,因此存储电容的加入不影响比较器的带宽和动作速度。(2)提出了一种消除周期性失码现象的随机码校准算法由于寄生电容,单位桥电容结构SAR-ADC会出现周期性的失码现象,影响SAR-ADC的转换精度。本文提出了一种消除周期性失码现象的随机码校准算法,通过将相邻的码字以1/2的概率分配给丢失码字,从而补偿丢失的码字。该校准算法能够消除周期性失码现象且具有简单易实现的特点。(3)提出了一种斜坡数字逐位校准算法由于当前的数字校准算法在校准时高位权重和低位权重会被同时校准,从而出现不收敛的现象,这就需要在校准精度和校准时间之间进行折中。本文提出了一种斜坡数字逐位校准算法,在校准阶段采用单调递增的斜坡信号作为输入信号,对SAR-ADC的输出数字码从低位到高位进行数字逐位校准。与传统的亚二进制电容结构SAR-ADC数字校准算法相比,本文提出的斜坡数字逐位校准算法具有简单、稳定和校准速度快的特点。本文分别针对CZT探测器系统的不同应用领域,基于所提出的创新技术,研发成功三款SAR-ADC芯片,具有精度高、抗辐照和多通道集成的特点。本文的研究成果对研发辐射探测器的前端读出系统具有重要的理论意义和实用价值。更多还原

【Abstract】 Cadmium Zinc Telluride(CZT)detector is considered as one of the most promising next generation semiconductor radiation detectors.The imaging systems based on the CZT detector have a wide range of applications,such as space exploration,biomedical imaging,radioactivity detection,safety inspection,and so on.The front-end readout system is the key device of the CZT detector system,the function of which is to amplify,shape and digitize the weak electrical signals generated by the CZT detector.The analog to digital converter(ADC)is an important part in the front-end readout circuit,which is required to have the features of high resolution,high sampling rate,small area,less power dissipation and radiation tolerance.In this thesis,the SAR-ADC(Successive Approximation Register-ADC)aimed to use in the CZT detector imaging systems is designed and implemented,the main contributions and innovations are summarized as follows.1 Main research works(1)Research and design of a capacitor-resister hybrid SAR-ADC chipAimed to use in the CZT detector system for portableγ-ray spectrometer,a 12-bit 1 MS/s capacitor-resister hybrid SAR-ADC chip has been designed and implemented.This SAR-ADC is with simple circuit structure and is easily implemented.The DAC is composed of 6-bit C-DAC and 6-bit R-DAC,in which a good tradeoff between the conversion precision and the power dissipation is achieved.In addition,the 6-bit C-DAC is realized by unit capacitor array so as to improve the linearity of the SAR-ADC.The measurement results of the chip indicate that,no missing code exists,and the ENOB can reach up to 10.94-bit with power dissipation of 10 mW.The active area of chip is 1.274 mm~2.(2)Research and design of a unit bridge capacitor structure SAR-ADC chipAimed to use in the CZT detector system for PET biomedical imaging,a 12-bit 1 MS/s unit bridge capacitor structure SAR-ADC chip has been designed and implemented.This SAR-ADC has the features of low power and small die area.Compared with the traditional fractional bridge capacitor C-DAC,the adoption of unit bridge capacitor can improve the matching precision of bridge capacitor.Besides,in order to eliminate the phenomenon of periodic missing codes,the code-randomized calibration technique is proposed for this SAR-ADC.The measurement results of chip indicate that,there are no missing codes after the calibration,and the ENOB can reach up to 11.00-bit with power dissipation of 5 mW.The active area of chip is only 0.943 mm~2.(3)Research and design of a sub-radix-2 capacitor structure SAR-ADC chipAimed to use in the CZT detector system for the space exploration of X/γ-ray,a 12-bit1MS/s new ramp digital bit-by-bit calibration sub-radix-2 capacitor structure SAR-ADC chip has been designed and implemented.This SAR-ADC has the features of low power,small die area and radiation tolerance,which is suitable for multi-channel integration.In order to reduce the influence of capacitors mismatch on the conversion precision of SAR-ADC,a ramp digital bit-by-bit calibration algorithm is proposed.The measurement results of chip indicate that,there are no missing codes after the calibration,and the ENOB can reach up to 10.88-bit with power dissipation of 3 mW.The active area of chip is only 0.687 mm~2.The above three SAR-ADC chips are implemented using TSMC 0.35μm CMOS commercial process.(4)The radiation-hardened design in SAR-ADC chipConsidering the SAR-ADC chip developed in this thesis will be used in the space exploration of X/γ-ray,the radiation-hardened design is completed in both the circuit-level and layout-level to increase the radiation-hardened ability of it.To eliminate the effects of threshold-voltage shift in CMOS transistors caused by the total ionizing dose effects(TID),the self-cancellation technique of offset voltage is adopted in the comparator design.To eliminate the effects of single-event upset(SEU),the resistance-delay circuit is added in the latch of comparator,and the dual interlocked storage cell(DICE)is used in the shift registers.To eliminate the effects of single-event latch-up(SEL),two radiation-hardened design technologies are adopted in the layout design of the digital standard cells,one is adding the P+and N+guard rings in NMOS and PMOS transistors,the other is enlarging the distance between the PMOS and NMOS transistors.2 Main innovations proposed(1)A self-cancellation technique of offset voltage for high-speed comparator.The offset voltage of comparator influences the conversion precision of ADC seriously.For the traditional offset voltage cancellation technique,since the offset storage capacitors are cascaded on the signal pathway,thus the bandwidth and the response speed of comparator is reduced.A self-cancellation technique of offset voltage in high-speed comparator is proposed in this thesis,in which the offset storage capacitors are removed to the two ends of output loads,and therefore no any capacitor is introduced on the signal pathway.As a result,adding offset storage capacitors do not influence the bandwidth and response speed of the comparator.(2)A code-randomized calibration algorithm to eliminate the periodic missing code phenomenon.Due to the influences of parasitic capacitors,the periodic missing code phenomenon occurs often in the unit bridge capacitor structure SAR-ADC,which degrades the conversion precision of SAR-ADC.In this thesis,a code-randomized calibration algorithm is proposed to eliminate the periodic missing code phenomenon by means of compensating the missing code with the probability of 1/2 by adiacent codes.The proposed calibration algorithm which can eliminate the periodic missing code is simple and can be easily realized.(3)A ramp digital bit-by-bit calibration algorithm.In the traditional calibration algorithm of sub-radix-2 capacitors structure SAR-ADC,the nonconvergence situation may occur,since the weights of all-bits of SAR-ADC are calibrated simultaneously.Thus,the tradeoff between the calibration precision and calibration time is required.In order to overcome above issue,a ramp digital bit-by-bit calibration algorithm is proposed in this thesis.In the calibration stage,a linearly increasing ramp signal is used as the input signal of SAR-ADC,and the output digital codes of SAR-ADC are calibrated bit-by-bit from lower weight bits to higher weight bits,in which the calibrated lower weight bits are utilized for the higher weight bits calibrations.Therefore,the proposed calibration algorithm is simpler,more stable,and faster than the traditional approaches.In this thesis,for the different application fields of CZT detector system,three kinds of SAR-ADC chips were developed successfully based on the innovative technologies proposed,which are with the features of high-precision,radiation tolerance and multi-channel integration.And the achievements obtained in this study have important theoretical significance and pratical values for developing the front-end redout system of the radiation-detectors.更多还原