【作者】 王刚；

【导师】 陈贺新；

【作者基本信息】 吉林大学 ， 通信与信息系统， 2017， 博士

【摘要】 国际视频压缩编码标准H.264/AVC和H.265/HEVC运用了混合视频编码技术(运动补偿预测技术和DCT编码技术)。在混合视频编码技术中,编码器的核心算法是帧间预测,利用帧间预测可去除视频序列中时间域的冗余信息。它包括整像素运动估计和分像素运动估计。在运动估计中,利用像素间的相关性进行分像素值的内插可提高运动矢量估计的准确性,从而使运动补偿过程产生较小的残差数据。实验证明,高精度的运动补偿能够提高视频编码的压缩效率,在提高运动预测性能的同时,也带来运算量大和存储操作频繁等问题。滤波器阶数决定了参考数据的读入量,如何在保证预测准确性前提下,降低插值复杂度是目前要研究的问题。本文以国家自然科学基金项目“基于灵活四叉树模型和改进DCT的高效率视频编码研究”和吉林省教育厅“十三五”科学技术研究规划项目“面向HEVC的滤波算法及DCT优化研究”为依托,分析了视频压缩编码理论技术研究现状、国际视频编码标准的发展过程以及视频图像插值的方法及原理。并对分像素运动补偿技术及VLSI结构设计进行深入研究。本文在H.264/AVC标准、H.265/HEVC标准的分像素插值滤波优化算法、自适应分像素插值算法和面向HEVC的高效插值滤波VLSI架构设计四个方面进行深入研究,并取得如下成果:(1)改进的H.264分像素插值滤波算法为了进一步提高H.264/AVC标准视频编码的效率,提出了一种改进的H.264分像素插值滤波算法—即滤波系数可变、系数和不变的分像素插值算法,将H.264/AVC标准中6阶滤波器替换为4阶滤波器。算法利用三次卷积插值法求得插值滤波器系数,利用方向性插值滤波器获得分像素位置的采样,并在编码GOP结构设定进行优化。实验结果表明:在复杂度方面,相对H.264标准的算法,本文算法降低了19%空间复杂度,减小存储访问量,但计算复杂度有所增加。在编码性能方面,相对H.264标准的算法,本文算法使PSNR值平均提高0.38dB,并使比特率平均降低了4.74%。所以,本文提出的算法对不同运动程度的视频序列编码性能均有提高。(2)基于自适应滤波器的分像素插值算法针对不同分辨率的视频序列采用相同阶数滤波器进行分像素插值不能进一步提高编码性能的问题,提出了基于自适应滤波器的分像素插值算法。算法根据设定的3个不同视频序列分辨率区域,自动选择不同阶数的插值滤波器(即分辨率R≥2560×1600,选择4阶滤波器;1280×720≤R<2560×1600,选择6阶滤波器;R<1280×720,选择8阶滤波器。);在3个不同分辨率视频序列区域内,根据像素间相关性将高阶插值滤波器替换为低阶插值滤波器,实现滤波器的自适应选择。在3个不同分辨率视频序列区域内进行分像素运动补偿插值,利用原始图像代替1/2像素图像,将得到的1/2像素图像代替1/4像素图像,实现AF_FIA算法优化。实验结果表明:在空间复杂度方面,相对于HEVC标准的滤波器,4阶滤波器可以降低32%的空间复杂度,6阶滤波器可以降低16%的空间复杂度。在计算复杂度方面,4阶滤波器和6阶滤波器相对于HEVC的滤波器的乘法和加法都有大幅度降低,尤其4阶滤波器的乘法数和加法数不到HEVC的1/3左右;8阶滤波器的空间复杂度与HEVC相同,计算复杂度有所提升,但对于低分辨率的视频编码影响不大。在编码性能方面,无论是采取IBBP编码结构还是IPPP编码结构,相对HEVC标准算法,本文提出的算法提高编码增益,降低码率,具有较好的鲁棒性。(3)基于HEVC的自适应插值滤波算法为了进一步提高自适应分像素插值算法的视频图像质量,降低计算复杂度,提出了基于HEVC的自适应插值滤波算法。该算法在新编码标准H.265/HEVC视频编码框架进行编码来提高视频编码效率,通过滤波器系数对称优化,降低了码流所需滤波器系数和解码计算复杂。实验结果表明:在复杂度方面,相对NS_AIF算法和S_AIF算法,AIF_HEVC算法所需插值滤波器系数大幅度降低,与MD_AIF算法滤波器系数相当,但高于D_AIF算法。相对S_AIF算法,D_AIF算法,MD_AIF算法,AIF_HEVC算法大大降低了计算复杂度。在编码性能方面,无论是采取IBBP编码结构还是IPPP编码结构,相对D_AIF算法、S_AIF算法、CMD_AIF算法和AF_FIA优化算法,AIF_HEVC算法提高编码性能,具有较好鲁棒性。(4)面向HEVC的高效插值滤波VLSI架构设计针对数据高吞吐率和访存量高是HEVC标准解码器的瓶颈问题,提出了一种面向HEVC的高效率分像素插值滤波VLSI架构设计。首先利用滤波器系数反转对称性,设计了可复用8阶滤波器结构;之后提出了并行化设计和流水线结构分像素插值计算方案;最后在传统的单输入通道插值器基础上,提出两路并行的8输入插值器。测试结果表明:本设计插值结构在处理时间和吞吐量方面都优越于其它设计方法,在较低的工作频率就能完成相同高清/超高清视频实时传输,从而降低了传输功耗。本文所提出8输入双通道插值滤波结构能够在频率34.2MHz下完成1920×1080@30fps视频解码需求。同时,能够满足3840×2160@60fps视频的实时传输。更多还原

【Abstract】 The hybrid video coding technique(motion compensation prediction technique and coding technique based on DCT)is applied in the international Video Compression Coding Standard of H.264/AVC and H.265/HEVC;in hybrid video coding technique,the core algorithm of encoder is inter-frame prediction.The inter-frame prediction can be used to wipe out the redundant information of time domain in video sequence,which includes integer pixel motion estimation and fractional pixel motion estimation.In motion estimation,the correlation between pixels can be used to complete the interpolation of fractional pixel value to improve the veracity of motion vector estimation so that smaller residual data can be generated in motion compensation process.Experimental results show that the high-precision motion compensation can enhance the compression efficiency of video coding as well as the motion estimation performance,and meanwhile lead to heavy computation and frequent memory operation.The order of filter can determine the read-in amount of reference data and how to reduce the complexity of interpolation on the premise that the prediction accuracy is guaranteed has become a major problem.In this thesis,depending on the “Study on High Efficient Video Coding Based on Flexible Quad-tree Mode and Improved DCT”of National Natural Science Foundation of China and the “Study of Filtering Algorithm and DCT Optimization Facing HEVC” of Science and Technology Research Project of the 13 th Five Year of Jilin Provincial Education Office,the research status for the theories and techniques of video compression encoding,the development process of international video coding standard and the methods and principles for video image interpolation are analyzed and the sub-pixel motion compensation technique as well as the VLSI structure design are studied profoundly to lay the foundation for the further constructing more efficient H.265/HEVC video coding.The sub-pixel motion compensation technique can increase encoding and decoding computation and memory access complexity while improving video coding performance.In this thesis,the algorithm for sub-pixel interpolation filtering optimization of H.264/AVC and H.265/HEVC standard,the high efficient interpolation filtering of HEVC motion compensation and Adaptive Interpolation Filter and VLSI structure design are lucubrated and the following results are obtained:(1)Improved H.264 sub-pixel interpolation filtering algorithm In order to improve the efficiency of video coding of H.264/AVC standard,the improved H.264 sub-pixel interpolation filtering algorithm is put forward,namely sub-pixel interpolation algorithm whose filter coefficient is variable and coefficient sum is invariable and the sixth order filter is replaced by fourth order filter.In this algorithm,cubic convolution is applied to acquire the coefficient of interpolation filter,directional interpolation filter is used to obtain the sample of sub-pixel position and optimization is done while encoding GOP structure.The experimental results show that in terms of complexity,compared with H.264 standard algorithm,the algorithm in this thesis reduces the space complexity by 19% and decreases the visitor volume,but increases the computation complexity.In terms of coding performance,compared with H.264 standard algorithm,the algorithm in this thesis enhances PSNR value by 0.38 d B and reduces bit rate by 4.74% averagely.Hence,the algorithm posed in this thesis can improve video sequence coding performance of different movement degree.(2)Sub-pixel interpolation algorithm based on adaptive filterSince the coding performance can not be further improved if the filter of same order is used to interpolate for the video sequences of different resolutions,the sub-pixel interpolation algorithm based on adaptive filter is put forward.In the algorithm,the interpolation filters of different orders(namely,resolution ratio R≥2560×1600,select fourth order filter;1280×720≤R<2560×1600,select sixth order filter;R < 1280×720,select eighth order filter.)can be selected automatically according to 3 given video sequences;within the video sequence area of 3 different resolution ratios,the high order interpolation filter can be replace by low order interpolation filter according to the correlation between pixels to realize the adaptive selection of filter.Conduct sub-pixel motion compensation interpolations in 3 video sequence areas with different resolutions and use original images to replace half pixel pictures and the acquired half pixel pictures to replace quarter-pixel pictures so as to realize AF_FIA algorithm optimization.The experiment results show that compared with filter of HEVC standard,the fourth order filter can reduce 32% and sixth order filter can reduce 16% of space complexity.In terms of computation complexity,both fourth and sixth order filters reduce sharply the multiplication and addition compared with HEVC;in particular,the amount of multiplication and addition is less than 1/3 of HEVC;the space complexity of eighth order filter is same to HEVC,and the computation complexity is improved to some extent with small influence on video coding of low resolution.In terms of coding performance,both the algorithm by IBBP and IPPP coding structures has improved the peak noise rate and coding performance with good robustness and reduced bit rate compared with HEVC standard algorithm.(3)Adaptive Interpolation Filter Algorithm Based on HEVCIn order to further improve video quality of adaptive sub-pixel interpolation algorithm and reduce computation complexity,adaptive interpolation filter algorithm based on HEVC is put forward.This algorithm encodes within the video coding framework of new coding standard H.265/HEVC to raise efficiency of video coding;through the symmetric optimization of filter coefficients,the filter coefficients demanded by code stream and the complexity of decoding computation are reduced.The experimental results show that in terms of complexity,compared with NS_AIF algorithm and S_AIF algorithm,the interpolation filter coefficient demanded by AIF_HEVC algorithm is reduced sharply,equivalent to filter coefficient of MD_AIF algorithm,but higher than D_AIF algorithm.Compared with S_AIF algorithm,D_AIF algorithm and MD_AIF algorithm,the computation complexity of AIF_HEVC algorithm is reduced greatly.In terms of coding performance,compared with D_AIF algorithm,S_AIF algorithm,CMD_AIF algorithm and AF_FIA optimization algorithm,the coding performance of AIF_HEVC algorithm is improved with good robustness no matter IBBP encoding structure or IPPP encoding structure is applied.(4)VLSI structure design of high efficient interpolation filtering for HEVCSince the high data throughput and memory access amount are the bottleneck problems for the decoder of HEVC standard,a VLSI structure design of high efficient sub-pixel interpolation filtering facing HEVC is put forward.Firstly,the reusable eighth order filter structure is designed based on the inversion symmetry of filter coefficient;secondly,the parallel design and sub-pixel interpolation calculation scheme of pipeline architecture are put forward;finally,the two parallel 8 input interpolator are posed based on the traditional single input channel interpolator.The test results show that the interpolation structure in terms of processing time and throughput are superior to other design methods,and can achieve the same HD/Ultra HD video real-time transmission at a lower operating frequency,thereby reducing the transmission power consumption.The proposed 8-input dual-channel interpolation filter structure can be completed at a frequency of 34.2MHz at 1920×1080 @ 30 fps video decoding needs.At the same time,to meet the 3840×2160 @60fps real-time video transmission.更多还原