【作者】 秦鹏；

【导师】 周健军；

【作者基本信息】 上海交通大学 ， 电子科学与技术， 2014， 博士

【摘要】 信道是通信系统中最宝贵的资源之一。由于越来越多的新通信协议正在占用低频信道,高频信道应用正逐渐成为新时代通信系统的解决方案。作为通信系统的物理基础,射频技术也在向更高频率的应用不断发展。高频通信系统对于宽频带范围和高信噪比的要求,给应用在此类系统中的射频接收机以及其关键组成部分——频率合成器的设计带来了挑战。本论文针对应用于X波段(8-12GHz)频率合成器在频率范围、相位噪声和锁定时间方面的设计难点,提出一系列提升频率合成器性能的创新型解决方案,在电路设计过程中,完成了以下研究:首先,针对高频通信系统中接收机的性能要求,以卫星广播低噪声下变频器为应用背景,选择适用于X波段的锁相环型频率合成器架构,制定系统的性能指标,将系统指标在各模块之间合理分配。通过建立行为级仿真模型,验证系统参数的合理性。其次,为提升X波段频率合成器在低功耗和低噪声方面的性能要求,在电路模块设计时,提出了许多基于65nm CMOS工艺的创新性解决方案。这些技术对锁相环型频率合成器的模块设计都具有指导意义。本文提出了应用于高频宽频带压控振荡器频率自检测辅助的噪声抑制技术、调谐电压拓展技术以及低噪声电压偏置技术,在不增加电路代价的情况下降低了频率合成器的带外相位噪声。本文同时提出了一种低噪声、高电源抑制比的晶体振荡器,降低了频率合成器的带内相位噪声。接着,针对传统自动频率校准速度慢的缺点,提出了基于多相位时钟采样的自动频率校准加速算法,达到了极高的校准速度与精度。与此同时,本设计创新性的将原本用于模拟环路中的多模分频器,在校准过程中变为多相位生成器使用,在不增加电路面积以和功耗的前提下,最大限度的利用了分频器功能。最后,在65nm CMOS工艺下实现了综合以上功能的全集成高性能X波段频率合成器,核心电路面积为0.2mm2,工作频率覆盖9GHz-12GHz,任意输出频点在1kHz-10MHz范围内积分相位噪声小于-37dBc,积分相位误差小于0.8°,在1MHz频偏处的相位噪声小于110dBc/Hz,电流功耗小于33mA,频率校准时间不超过1.44μs,任意频率跳变之后的锁定时间均小于20μs,完整的证明了前述设计方法的有效性。与国内外最新发表记录比较,在电路面积,功耗以及噪声性能等方面均已达到领先水平。更多还原

【Abstract】 Channel is one of the most valuable resources in communication system. Since low frequency channels are occupies by more and more communication protocols, high frequency channel application is becoming a resolution for modern communication systems. As a physical understructure of communication systems, the development of radio frequency(RF) techniques also aims at higher frequency applications. High frequency communication systems require wide frequency range and high signal to noise ratio(SNR), which brings challenge to design of RF receivers and also its critical component – frequency synthesizer for high frequency applications.This thesis aims at satisfying the stringent requirement of frequency range, phase noise, and settling time for X-band(8-12GHz) frequency synthesizer applications. A series of innovative designs are proposed to improve synthesizer performance, and the following works are completed during circuit implementation:At first, phase locked loop(PLL) based frequency synthesizer suited for X-band application is adopted to satisfy the performance requirement of receivers which are used in high frequency communication systems. Performance specifications is made to the proposed frequency synthesizer and allocated to all building blocks, using the low noise down-converter(low noise block, LNB) for satellite broadcasting system as a design objective. Validity of system parameters is demonstrated through behavior level simulations.Second, in order to improve low power and low noise requirements of X-band frequency synthesizers, some 65 nm CMOS technology based circuit implementation methods are proposed during block design. A voltage controlled oscillator(VCO) phase noise optimization method based on frequency calibration, tuning voltage range extension and low noise bias voltage is proposed for wide band VCOs, which reduces out-of-band phase noise of the proposed frequency synthesizer. A low noise, high power supply rejection ratio current bias is proposed to improve phase noise performance of the proposed crystal oscillator(XO), which reduces in-band phase noise of the proposed frequency synthesizer.Third, a multi-phase clock sampling based automatic frequency calibration(AFC) acceleration algorithm is proposed to overcome the low speed disadvantage of conventional AFCs. Very fast AFC speed and high calibration accuracy is achieved. At the same time, the multi-mudulus frequency divider is proposed to be reused during calibration process, as a multi-phase generator. Divider function is fully used without adding new circuit and power dissipation.At last, a frequency synthesizer suitable for X-band communication system is implemented under 65 nm CMOS technology with 0.2mm2 core circuit area. Frequency range of the proposed frequency synthesizer covers 9GHz to 12 GHz and its phase noise is less than-37 dBc for all output frequency, integrated from 10 kHz to 13 MHz frequency offset, which is less than 0.8° calculated as phase error. Spot phase noise at 1MHz frequency offset is less than 110dBc/Hz. Total current consumption is less than 33 mA. AFC time is less than 1.44μs and the PLL settling time is less than 20μs. Advantages of the proposed techniques are demonstrated through the experimental result quoted above. Performance of proposed frequency synthesizer is comparable among international academic publications.更多还原