【作者】 李靖；

【导师】 刘洋；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2014， 博士

【摘要】 随着集成电路制造工艺水平的进一步提高,数字信号处理的速度飞速发展,作为模拟域和数字域桥梁的模数转换器(ADC),整机系统对其转换速率和精度也提出了更高的要求。在中频及射频采样下,超高速ADC广泛应用于宽带通信、仪器仪表、测试系统、雷达、软件无线电等领域,具有重要的民用价值和战略意义。常规的单核高速ADC结构经过国内外学者的多年研究,基础理论和实现方法已较为完善,其转换速率和精度难以跟随制造工艺的发展而快速提高。时间交织结构利用时钟分相技术,控制多个并联的高速ADC交替工作,从而在保持ADC精度的同时实现ADC转换速率的倍增。该方法是实现超高速模数转换的有效方法之一,并联的ADC个数越多,能实现的转换速率越高。但是由于器件失配、芯片内温度和应力分布不均等因素的影响,各通道的ADC间存在增益失配、失调失配、采样时间失配和采样带宽失配等误差,影响并制约超高速时间交织ADC的性能。同时,高速采样时钟的精度和多相时钟的稳定性也将对ADC的性能产生影响。针对上述问题,本文进行了深入的研究和讨论,包括通道间失配误差的分析与校正,高速低抖动时钟的设计,多相时钟发生器的设计与校正和双通道时间交织ADC的设计与物理实现,主要的研究工作和创新如下:1.通道间失配误差的分析与校正:对通道ADC间的失配误差进行分析和讨论,建立失配误差模型,基于MATLAB仿真工具定性分析失配误差的对ADC性能的影响。对于失调失配误差和增益失配误差,采用前台和后台相结合的均衡化技术对两种误差进行校正。而对于采样时间失配误差,本文首先提出了一种全局时钟采样技术,利用全局时钟采样解决时钟失配问题。随后介绍了一种基于通道间数字输出差值的自适应后台校正算法,该方法利用数字域与模拟域相结合的方式,既减小了纯数字式校正的硬件开销,也降低了模拟电路的复杂度,为通道间的时钟失配误差校正提供了一种优良的解决方案。在此基础上,为了进一步扩展校正方法的适用频率范围,提出了一种基于导数的自适应校正技术。该技术通过数字输出信号的导数来估算时钟失配误差,其准确度更高,在整个奈奎斯特范围内均可以有效检测并校正时钟失配误差。2.高速低抖动时钟发生器的设计与实现:针对纳米工艺下低压薄栅晶体管的漏电问题,建立了漏电模型,提出了一种电压-电压补偿电路,减小晶体管漏电对电荷泵锁相环输出时钟的贡献。在此基础上,设计了1.6 GHz的时钟发生器,通过优化环路稳定性和环路噪声,输出时钟抖动仿真结果为2.27 ps。3.多相时钟发生器的设计与实现:基于延迟锁相环技术设计了四相时钟发生器,输出时钟频率为400 MHz,占空比为50%。针对多相时钟间的相位失配问题,提出了一种后台自适应校正技术。该技术利用电荷泵和滤波电容检测时钟间的延迟时间误差,并通过模拟缓冲器调节对应时钟的延迟时间,从而实现时钟间失配误差的校正。在65 nm标准CMOS工艺下,进行了流片验证,测试结果显示延迟锁相环正常锁定,输出时钟正常,校正后输出时钟延迟时间从690 ps减小为630 ps,接近标准值625 ps,实现了时钟间失配误差的校正。4.双通道时间交织ADC的设计与实现:基于流水线ADC的功耗分析,确定12位800 MSPS ADC采用双通道时间交织结构实现,单通道ADC的级精度为2.5位。在运放的设计过程中,采用厚栅和薄栅MOSFET相结合的方式,提高运放的输出摆幅和带宽。芯片内还集成了带隙基准偏置电路、低压差分输出接口电路(LVDS)、通道间失配误差校正逻辑等功能模块电路。在65 nm标准CMOS工艺下,进行了流片验证,芯片面积为5×3 mm2,整体芯片功耗为1200 mW。测试结果显示,ADC工作状态正常,对输入信号进行正常转换并通过LVDS接口输出,失配误差校正技术能对通道间的失配误差进行有效校正,校正后,双通道时间交织ADC的SFDR为58.9 dB,SNDR为49.5 dB,有效位7.9位。更多还原

【Abstract】 With the critical dimension scaling down according to the Moore’s law, the speed of digital signal processing is highly improved. Analog-to-digital converter(ADC) works as the bridge between analog signal and digital signal. Its performance to be higher precision and higher speed is desired by the whole system. Under the sampling frequency of intermediate frequency(IF) and radio frequency(RF), high-speed ADC is widely used in wideband communication, instrument, measurement, radar, software radio and so on. It has high military and civil value. The conventional high-speed ADC architectures with single core are studied by researchers at home-and-broad for years. Its fundamental theory and realization method are highly mature. The converting speed and resolution are close to the limitation and it is hard to further improve with the improvement of process.Time-interleaved architecture utilizes the clock distribution technique to control several ADCs working one-by-one, and thus realize the multiplication of the ADC converting rate. This architecture is one of the most efficient ways to realize the ultra-high-speed ADC. Theoretically, the available converting rate is unlimited. However, because of the device mismatch, temperature misdistribution and stress misdistribution in chip, the mismatches among channels will influence and limit the performance of the time-interleaved ADC(TIADC). The mismatches contains offset mismatch, gain mismatch, timing mismatch, bandwidth mismatch and so on. What’s more, both the precision of the high-speed clock and the stability of the multi-phase clock will affect the TIADC’s performance either. In this paper, the above problems are deeply studied. The main work and innovation are listed below:1. Analysis and calibration for the mismatches among channels: The mismatch model is firstly built based on the analysis of the mismatches and the influence on the ADC’s performance is demonstrated by MATLAB. Among the mismatches, offset and gain mismatches are calibrated by the equalization technique in foreground and background. For the timing mismatch, a global sampling technique is firstly proposed and expected to eliminate the timing mismatch entirely. Then, an adaptive background calibration method based on the digital output difference value between adjacent channels is introduced. It is a combination of digital filed and analog filed, and thus reduces the hardware cost in digital calibration method and also the complication in the analog circuit. It provides an advanced solution to mitigate the timing mismatch. And on this basis, an improved calibration by the derivative of the digital output is proposed to enlarge the applicable frequency range. This method utilizes the derivative of the digital output to estimate the timing mismatch and is with much higher precision. It is effective to detect and calibrate the timing mismatch in the entire Nyquist range.2. Design and realization of the high-speed and low-jitter clock generator: A gate leakage model is proposed for the low-voltage and thin-gate MOSFET in nano-meter process. To mitigate its contribution on the charge-pump phase-locked loop(PLL), a voltage-to-voltage circuit is introduced. And on this basis, a clock generator with output frequency of 1.62 GHz is designed. With the optimization of loop stability and loop noise, the jitter performance of the output clock is 2.27 ps.3. Design and realization of the multi-phase clock generator: A four-phase clock generator is designed based on the delay-locked loop(DLL). It works at a frequency of 400 MHz with a duty cycle of 50%. To solve the phase mismatch among clocks, an adaptive background calibration technique is proposed. It utilizes the charge pump and filter capacitor to detect the phase mismatch and realize the calibration by regulating the analog delay buffer. The design is realized under 65 nm standard CMOS process. The test results show that the DLL is locked and output the multi-phase clock correctly. After the calibration, the delay time is reduced from 690 ps to 630 ps which is close the standard value of 625 ps.4. Design and realization of the two-channel TIADC: For a 12-bit 800 MSPS ADC, a two-channel time-interleaved architecture is adopted based on the power analysis in pipelined ADC. The stage resolution is 2.5 bits. When designing the high-performance amplifier, thin-gate MOSFETs are widely used to enlarge the output swing and bandwidth. Bandgap reference, low-voltage-differential signaling(LVDS), mismatch calibration circuits are integrated. The design is realized under 65 nm CMOS technique with a core area of 5×3 mm2. The test results show that the proposed calibration techniques are effective to reduce the mismatches. The dynamic performances of the TIADC are: SFDR is 58.9 dB,SNDR is 49.5 dB and ENOB is 7.9 bits.更多还原