【作者】 王卓；

【导师】 张波；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2015， 博士

【摘要】 SOI(Silicon On Insulator,绝缘体上硅)高压LDMOS(Lateral Double-diffused Metal Oxide Semicondutor,横向双扩散金属氧化物半导体)器件具有低功耗、高频率、高集成度等特点,广泛用于智能功率集成电路,如汽车电子、医疗电子、智能家电和航空航天等领域。相比厚层SOI LDMOS,薄层SOI LDMOS具有良好的工艺兼容性和较少的寄生效应。因此,薄层SOI高压LDMOS在功率集成电路,特别是功率开关和驱动集成电路中有着良好的应用前景。但是由于背栅偏置的原因,薄层SOI P型高压LDMOS器件的特性受到严重影响,相比N型器件,其RESURF(REduced SURface Field,降低表面电场)效应被抑制,较难实现高的耐压。同时受到介质层电场限制,SOI高压LDMOS器件击穿电压很难突破600 V,阻碍了其在更高电压的集成电路中的应用。目前国际上研究集中在3μm以上厚层SOI高压LDMOS,对1.5μm以下的薄层SOI高压LDMOS鲜有研究,尤其是P型LDMOS(PLDMOS)。迄今的研究,大部分耐压模型针对厚层SOI高压LDMOS,对薄层SOI高压LDMOS也涉及较少。本文基于电场调制理论,研究了薄层SOI高压LDMOS背栅效应及耐压特性,建立了背栅耐压模型和超薄SOI横向线性变掺杂(Variation of Lateral Doping,VLD)LDMOS耐压模型,并提出两类新的器件结构。主要研究工作如下:1.提出SOI PLDMOS背栅耐压模型。针对SOI PLDMOS固有的背栅效应,提出了背栅耐压模型,给出背栅穿通击穿的判据。模型揭示了SOI高压PLDMOS背栅穿通机理,得到背栅电压、n阱浓度和pf区结深之间的关系。当穿通击穿判据条件满足时,背栅穿通击穿就会发生。该背栅模型适用于所有SOI PLDMOS,具有普适性。同时基于背栅模型,对1.5μm厚SOI PLDMOS耐压特性进行分析,优化结构参数,使其避免发生背栅穿通。实验结果显示SOI PLDMOS在背栅电压-200 V时,击穿电压达到329 V。2.提出超薄层SOI高压VLD NLDMOS耐压模型。针对超薄层SOI高压VLD NLDMOS,提出了耐压模型,给出器件的RESURF条件。基于介质场增强理论,采用超薄漂移区来提高硅临界击穿电场,从而提高击穿电压。基于RESURF条件,对器件耐压和比导通电阻特性进行研究。实验结果显示,超薄层SOI高压VLD NLDMOS的漂移区厚度约为0.15μm,器件耐压达到644 V,比导通电阻为24.1Ω·mm2。3.提出两类新的器件结构。基于上述SOI高压器件纵向耐压机理,提出了两类新的器件结构。第一类从增加器件纵向耐压出发,提出了三种新器件:T-RESURF型SON LDMOS、PSUB型SOI VLD LDMOS和界面电荷岛型SOI LDMOS。相比传统SON结构,T-RESURF型SON LDMOS在保持相同耐压同时,比导通电阻降低了40.8%。第二类提出一种U型槽栅SOI MOSFET,利用积累层来降低比导通电阻,相比常规槽栅结构,比导通电阻降低了83%,突破硅极限。更多还原

【Abstract】 SOI(Silicon on Insulator) high voltage LDMOS(Lateral Double-diffused Metal Oxide Semicondutor) devices are widely used in smart power integrated circuits such as automotive electronics, medical electronics, smart appliance and aerospace. Compared with thick layer SOI LDMOS, thin layer SOI LDMOS provides good technology compatibility and less parasitic effects. Hence, thin layer SOI high voltage LDMOS devices have good prospects in power integrated circuits,expecially in power switching and driver. However, due to back gate bias, characteristics for the thin layer SOI P type high voltage LDMOS devices have been affected. Compared with the N type, RESURF(REduced SURface Field) is inhibited for SOI P type high voltage lateral devices, leading to a low breakdown voltage. Meanwhile, due to limited electric field in dielectric layer, breakdown voltage for thin layer SOI high voltage LDMOS devices is difficult to exceed 600 V, which hinders the application in integrated circuits with higher supply voltage. At present, the researches over the world focus on thick layer SOI high voltage LDMOS with exceeded 3-μm-thick SOI layer, and less care has been devoted to thin layer SOI LDMOS, of which the thickness of SOI layer is less than 1.5 μm, especially PLDMOS. In addition, most reported breakdown models are based on thick layer SOI LDMOS, but the thin layer one.Based on electric field modulation approach, back gate effect and block characteristics for thin layer SOI high voltage LDMOS are investigated. Back gate breakdown model and ultra thin layer SOI high voltage VLD LDMOS breakdown model are developed, and two type of novel device structures are proposed.Main works are list as below:1. Back gate breakdown model.Based on the intrinsic back gate effect for SOI PLDMOS, back gate breakdown model is proposed, which gives a criterion for back gate puch-through breakdown. The back gate breakdown voltage model reveals up the back gate punch-through breakdown mechanism for thin layer SOI PLDMOS, and obtains the dependence of back gate voltage on the impurity concentration of nwell and the junction depth of pf region. As the criterion is satisfied, back gate punch-through breakdown occurs. The proposed model can be applied to all SOI PLDMOS. Meanwhile, based on the model, the breakdown characteristic of SOI PLDMOS with 1.5-μm-thick SOI layer is investigated. The structure parameters are optimized to avoid punch-through breakdown. Experimental results show the breakdown voltage of the thin layer SOI PLDMOS reach 329 V with back gate voltage of-200 V.2. Breakdown model for ultra thin layer SOI high voltage VLD LDMOS.Breakdown voltage model for ultra thin layer SOI high voltage VLD LDMOS is proposed, which gives the RESURF condition. Based on enhanced dielectric field theory, ultra thin drift region is adopted to enhance critical breakdown electric field of silicon, resulting in a high breakdown voltage. Based on the RESUFR condition, the characteristics of breakdown voltage and specific on-resistance are investigated. Experimental results show that the breakdown voltage and specific on-resistance are 644 V and 24.1 Ω·mm2, respectively, for ultra thin layer SOI high voltage VLD LDMOS with 0.15-μm-thick SOI layer.3. Two type of novle device structures.Based on above vertical breakdown mechanism for SOI high voltage devices, two type device structures are proposed. The first type device is developed from the concept that improving vertical breakdown voltage, contains: T-RESURF SON LDMOS、PSUB SOI VLD LDMOS and SOI LDMOS with interface charge. Compared with conventional SON structure, specific on-resistance for T-RESURF SON LDMOS reduces by 40.8% which maintaining the same breakdown voltage. The second type device is SOI MOSFET with U type trench gate, developed from the concept of accumulation conduction. Compared with conventional SOI with trench gate, the specific on-resistance of SOI MOSFET with U type trench gate reduces by 83%, breaking silicon limit.更多还原