H.264/HEVC视频解码的VLSI结构及实现研究

【作者】 沈沙；

【导师】 曾晓洋；

【作者基本信息】 复旦大学 ， 微电子学与固体电子学， 2013， 博士

【摘要】 High Efficiency Video Coding (HEVC)是目前正在由MPEG和ITU两大标准组织联合制定的新一代视频编码标准,它的目标是在保持同等图像质量的前提下将码率在H.264/AVC的基础之上降低50%。为了达成这一目标,HEVC标准中采用了很多全新的编码工具：基于Quad-tree的图像分割方式、大尺寸离散余弦变换、离散正弦变换(DST)、全新环路滤波器等。这些新算法的引入大大提高了HEVC标准的编码压缩性能,但是这些新算法也对视频编解码器的VLSI实现架构提出了新的挑战。同时,在实际应用中新旧标准的更替是一个渐进的过程,在此过程中多种视频标准将会在一个较长时间内共存。因此,多标准融合的视频解码架构也有着非常广泛的实际应用需求。有鉴于此,本论文的主要工作与创新点体现于如下几个方面：1.深入研究了HEVC标准中设计的各种算法,包括CABAC,大尺寸离散余弦变换、离散正弦变换、环路滤波器等,针对各种新的算法提出了适用于多标准的VLSI实现架构。针对CABAC算法,提出了一种H.264和HEVC共享上下文模型存储空间的VLSI架构；针对大尺寸离散余弦变换,提出了一种同时支持多标准、多种变换尺寸的VLSI架构,此架构还可以以很小的硬件代价来实现HEVC标准中的4x4离散正弦变换；针对新的环路滤波器,提出了一种SAO滤波器与deblocking滤波器共享片上SRAM的架构,可以大大降低硬件资源开销。2.针对HEVC标准中全新的图像分割方式,提出了一种流水线粒度为32x32像素块的5级流水线架构。传统的视频编码标准都采用大小为16x16的宏块为单位进行图像分块,但是HEVC标准中分块大小最大为64x64。在研究了HEVC各模块的算法之后,本文提出了一种流水线粒度为32x32像素块的硬件架构。每一级流水线最大能处理32x32的像素块,这种基于32x32分块大小的流水线架构能够在不牺牲整体系统性能的前提下将硬件代价最小化。此架构不仅适用于HEVC,同样也适用于其他传统的视频编码标准。3.针对熵解码模块的瓶颈问题提出了一种异步流水线的架构。由于熵解码的串行特性,无论是CAVLC还是CABAC都容易成为整个系统的瓶颈,本文提出了一种异步流水线的架构,既可以大幅提高熵解码模块的吞吐率,又能保持整个系统的低功耗。更多还原

【Abstract】 High Efficiency Video Coding (HEVC) is the latest video coding standard which is jointly developed by the two standardization organizations (MPEG and ITU). Its target is to reduce 50% bitrate in comparison with H.264/AVC under the same picture quality. In order to achieve this goal, many new coding tools are used in HEVC:the Quad-tree based picture partitioning, large size discrete cosine transform, discrete sine transform and new in-loop filter etc. These new algorithm greatly improve the coding efficiency of HEVC. But they also bring new challenges for the VLSI architecture of a video codec. Moreover, it will be a progressive process to replace the previous standards with new one. The new standard will coexists with traditional standards for quite a long time. There is also a vast demands for a universal video decoding architecture which can support multi-standard.In order to accommodate these requirements, several novel innovations and contributions are presented as the following:1. Various new algorithms in HEVC are evaluated in depth, which include CABAC, large size discrete cosine transform, discrete sine transform and new in-loop filter. A novel VLSI architecture is proposed for CABAC, which can support a shared storage of context models for both H.264 and HEVC. A unified VLSI architecture is proposed to support DCT with various transform size used in different standards. 4x4 DST can also supported in this architecture with little hardware overhead. A shared-SRAM architecture is proposed to support the new in-loop filter, which can greadly reduce the hardware cost.2. A 5-stage pipeline architecture is proposed to support the new picture partitioning for HEVC. The pipeline granularity is 32×32 pixel block. The macroblock with size of 16x16 is the basic unit of picture partitioning for traditional video coding standards. But the partition block size can be up to 64x64 in HEVC. A 32×32 pixel block granularity based pipeline architecture is proposed in this thesis. Each pipeline can process a block of size up to 32×32. This proposed architecture can reduce the hardware cost without compromising the system performance. And it is applicable to traditional standards as well as HEVC.3. An asynchronous pipeline is proposed to solve the bottleneck of entropy decoding block. Due to the serial feature of entropy decoding, Either CAVLC or CABAC will become the bottleneck of the whole system. The proposed asynchronous pipeline in this thesis can improve the throughput of entropy decoding block and reduce the power dissipation of the system.更多还原