【作者】 陈宝君；

【导师】 唐祯安；

【作者基本信息】 大连理工大学 ， 电路与系统， 2012， 博士

【摘要】 在过去的四十多年中,集成电路的特征尺寸一直遵循着摩尔定律不断减小,性能在不断提高。二十世纪九十年代以前,集成电路中的金属互连线只被看做是简单参量的负载,而今随着互连线截面尺寸的急剧减小,简单参量已经不能描述互连线的特性。在器件特征尺寸进入纳米量级以后,工业界虽然普遍采用了铜/低K工艺和延迟优化技术来优化器件,但由互连线导致的信号延迟、能耗升高、带宽变窄等互连效应仍然非常突出。互连线的特性已成为当前制约集成电路和器件性能的主要瓶颈。因此互连线寄生参数(电阻、电感、电容和电导)的快速准确提取对高性能芯片的成功设计具有十分重要意义。互连线电容参数的提取方法已经较为成熟,本文重点研究互连线电阻(R)电感(L)参数的高效提取方法。矩量法是互连线电阻电感参数提取的经典方法,但基于矩形网格划分的传统矩量法仅适用于分析截面形状规则的理想导线,难以满足当前集成电路对互连线寄生参数提取的实际要求。另外,数值分析存在计算量大,有奇异点等问题,难以满足极大规模集成电路优化设计的要求,寻求集成电路模型的解析分析方法是必要的和急需的。本文以矩量法的理论和结果为基础,展开如下工作：(1)改进传统矩量法,使之可以计算截面为任意图形时互连线电阻电感参数,如粗糙表面互连线和梯形截面互连线等。(2)研究高阶基函数的矩量法,该方法减少传统矩量法中未知数个数,提高参数提取效率,并给出部分电阻电感矩阵元素解析式。(3)利用数值分析结果并结合优化方法如Levenberg-Marquardt等,得到不同结构导线的电阻计算解析公式,进一步提高芯片互连线参数提取效率。(4)使用最小二乘法结合拉格朗日方法得到了直流内部电感解析式,为在时域内分析趋肤效应提供了方便。(5)展开全部电感(内部电感+外部电感)的研究,使用泰勒级数展开法,得到了三维直流自感的解析式。本文提出的改进矩量法计算互连线电阻电感参数更加贴近实际情况,扩大了适用范围；高阶基函数矩量法提高了计算效率,与传统矩量法相比计算时间可节省90%以上；特定结构互连线电阻解析式的提出避免了数值方法计算效率低的问题,可以快速准确计算频变电阻值；直流内部电感解析公式为互连线宽频效应的研究提供了方便；三维直流自感解析式计算精确高,适用范围大,误差可以控制在0.2%以内,避免了数值计算中的奇异点问题。更多还原

【Abstract】 Moore law has driven the scaling of digital electronic devices dimensions and performances over the last40years. As a result, logic components in a microprocessor have shown dramatic performance improvement. On the other hand, an on-chip interconnect which was considered only as a parasitic load before1990s became the real performance bottleneck due to its extremely reduced cross section dimension. Now, on-chip global interconnect with conventional Cu/low-k and delay optimized repeater scheme faces great challenges in the nanometer regime, imposing problems of slower delay, coupling,higher power dissipation and limited bandwidth. On the otherside, how to get huge quarter of parasics parameter for the on-chip interconnects and do high capacity simulation is still the main task we are facing in the current verification.The method of moments (MOM) is a practice method for parasitic resistance and inductance parameter extraction of the interconnect. However, due to the rectangular discreditations used in the traditional MOM, there are some difficulties happened when using MOM to do extraction for a real whole chip interconnects, especially when technologic nodes bellows90nm. For example, the interconnect cross section may mot be a rectangular any more, the interconnect surface is rough surface. Based on the theory and result of MOM, the main topic includes:(1) improving the meshing generation the method of moments, introduced hybrid mesh (triangle+rectangle) to calculate the resistance and inductance parameter of any arbitrarily shaped section,(2) We explore the method of higher-order basis functions of MOM. The method reduces the number of unknowns in the traditional moment method and improves parameter extraction efficiency. Some analytic formulas for matrix elements of the electric resistance inductance are given.(3) Based on the results of numerical method, optimization method such as Levenberg-Marquardt are used to get analytical formulas of resistance for different structure interconnect, which further improve parameters extraction efficiency of on-chip interconnect.(4) Being influenced by the skin effect, the internal inductance of wires gradually decreases with increased frequency and internal inductance show the inductance frequency characteristic. In order to study the broadband effect of interconnect, internal inductance need to be studied. The least squares method and the Lagrangian method can be used to get the analytic form of internal inductance.(5) We study the whole inductance including internal inductance and external inductance and the analytic form of three-dimensional self-inductance of DC is educed by Taylor series expansion method.The improved MOM can be applied to analyze interconnect parasitic parameters of any arbitrarily shaped section and the result can approach the reality; the method of higher-order basis functions of MOM improves computational efficiency and it can save90%computational time at least compared traditional MOM; The proposed resistance analytic formulas can be used in three simple interconnect structures, greatly reducing the computation time; The internal inductance analytical formula is applied to the circuit model used to simulate the skin effect, which provides convenience in the time domain analysis of parasitic parameters. Meanwhile, the DC self-inductance analytical formula is proposed to avoid singular points in a numerical method.更多还原