【作者】 胡洋；

【导师】 冯丹；

【作者基本信息】 华中科技大学 ， 计算机系统结构， 2012， 博士

【摘要】 基于闪存的固态盘(Flash-based Solid State Disk:SSD)是近些年出现的一种新型存储设备。传统硬盘是由机械部件组成,而固态盘是由闪存芯片以一定结构组成的。相对于传统硬盘,固态盘在性能、能耗、可靠性、尺寸等方面有着明显的优势。现在,固态盘已逐渐成为便携计算机系统、桌面计算机系统、大型服务器系统、高性能计算系统的重要存储设备。但是闪存具有一些独特的读写特性,如：先擦后写、擦写次数有限、单个闪存卷片的读写性能有限,因此,对于固态盘组成、软件结构方面的设计应该是有针对性的,根据这些特性和外部负载的特点而进行特别“定制”。固态盘中有多个通道,每个通道由大量闪存芯片组成,闪存芯片具有多层结构,包括芯片-晶圆-分组。因此,固态盘有四个层次的并行结构：通道间并行—芯片间并行—晶圆间并行—分组间并行。有效利用这四个层次的并行是提高固态盘整体读写性能的关键。在固态盘中,闪存操作类型和分配方式影响着四层并行性的利用,如：多分组操作高级命令是利用分组间并行；交错操作高级命令是利用晶圆间并行；分配方式则是利用芯片间并行和通道间并行。但高级命令的使用有—定的限制条件,分配方式也具有多种不同的类型。所以,针对高级命令和分配方式与四层并行性之间的关系问题；针对四层并行性之间的优先级关系的问题,本文通过研究高级命令和分配方式的使用方法,来寻找四层并行之间的最佳优先级。实验数据显示,四层并行之间的最佳优先级是：通道间并行优于晶圆间并行；晶圆间并行优于分组间并行；分组间并行优于芯片间并行。固态盘中存在一个闪存转换层(Flash Translation Layer:FTL),用于翻译上层文件系统的读写命令、管理闪存的各种操作。FTL的优劣直接影响固态盘的性能、寿命、能耗的好坏。但是,现有的FTL通常无法兼顾这三个方面的要求。为了达到兼顾性能、寿命、能耗的目标,本文提出了两种不同的FTL算法,即三层页级映射算法、隐藏翻译过程映射算法。三层页级映射算法是利用固态盘的硬件结构,将一个分组分成多个部分,从分配的角度将整个固态盘从逻辑上看成三层结构：通道一块组一页。在这个算法中,当一组逻辑页被分配到一个块组时,这些逻辑页可以分配到块组中任意一个物理页。三层页级映射减少了映射表容量,却提供了类似于纯粹页级映射的性能,是一个高性能、低成本的映射方式。隐藏翻译过程映射算法是通过在传统固态盘结构中引入一个非易失存储器件(相变存储器),用以存放所有的页级映射关系,将读写映射关系数据的路径与读写用户数据的路径进行分离,达到了与页级映射相同的性能,减少了存放映射关系的内存容量,降低了内存的能耗,从而直接降低了固态盘的能耗。固态盘中内存具有两个主要用途：存放映射关系数据、存放缓存数据。本文提出了自适应的动态缓存管理算法。自适应的动态缓存管理算法包括两个模块：动态内存分区、动态闽值调整。动态内存分区算法是根据当前负载的特点,寻找到映射关系区域大小和数据缓存区域大小的最佳比例,动态调整内存的分区；动态阈值调整算法是根据近期写请求的密度,调整提前写回的缓存数据最的阈值,利用负载的请求间歇期、固态盘的内部空闲资源,根据阈值提前写回部分缓存数据,提前释放数据缓存空间。实验表明,相比传统缓存管理算法,自适应的动态缓存管理算法可以明显提高固态盘的读写性能、使用寿命。固态盘模拟器是进行固态盘研究的重要手段。固态盘模拟器SSDsim是基于“模块化、高准确性、可配置”这一目标而设计实现的,为研究者提供了测试固态盘的时间、寿命、能耗的模拟平台。它分成三个主要部分：硬件行为层、数据缓存层、闪存转换层。为了验证SSDsim的模拟结果的准确性,本文将它的测试结果与固态盘原型系统的测试结果进行比较,结果显示SSDsim的模拟绍i果和固态盘原型系统的真实结果基本一致。由此,可以看到SSDsim是一个高准确性的固态盘模拟工具。目前SSDsim已经开源。更多还原

【Abstract】 Flash-based Solid State Disk (SSD) is emerging as a promising nonvolatile storage device, which is composed by multiple flash chips. Compared with traditional Hard Driver Disk (HDD), SSD provides high-performance, low-energy consumption, high-reliability and so on. At present, SSDs have been widely employed in modern computing systems from low-end personal computers, medium-end servers to high-end high-performance supercomputers. There are two key and unique flash characteristics, namely, write-after-erase and erase cycle. A write operation can only change the value of each target bit from one to zero. Once a page is written, it must be erased, which means all bits are reset to one, before the next write operation can be performed on the same page. Each flash block has an upper limit of erase cycles before it is worn out. After wearing out, a block can no longer store any data. A typical MLC Flash has an erase-cycle limit of about 10K, while a typical SLC Flash has an erase-cycle limit of about 100K. For these intrinsic flash characteristics, some unique SSD hardware architectures and software systems are presented.There are four levels of parallelism inside SSDs, including channel-level parallelism, chip-level parallelism, die-level parallelism and plane-level parallelism. Utilizing these multi-level parallelism is the key point to improve the performance of SSD. In fact, several factors will impact the effectiveness of parallelism inside SSD, including flash advanced commands and allocation schemes. Flash advanced commands are provided by flash manufacturer for executing efficient read/write/erase operations. For example, multi-plane command utilizes plane-level parallelism by executing multiple read/write/erase operations concurrently in multiple planes; interleave command utilizes die-level parallelism by executing read/write/erase operations with pipelining style in several dies. There are several kinds of allocation schemes in SSD. Allocation schemes employ channel-level and chip-level parallelism. In this paper, I research the relationship between several levels parallelism and advanced commands, allocation schemes, determine the priority order of these levels that optimizes the performance and endurance of SSD. My experimental results show that the optimal priority order of parallelisms in SSD should be (1) the channel-level parallelism, (2) the die-level parallelism, (3) the plane-level parallelism and (4) the chip-level parallelism.Flash Translation Layer (FTL) is one of the most important components of SSD, whose main purpose is to perform translation from logical address to physical address adapting to the unqiue physical characteristics of flash memeory technology. Two novel FTL algorithms have been presented in this paper, namely three-level page-mapping FTL scheme and hiding address translation FTL scheme. The former utilizes the characteristics of SSD hardware system, divides a plane into several parts called block-group. A block-group has a fixed number of physical blocks. In this scheme, a series of logical pages are stored in a block-group. Inside the block-group, the mapping relationship between logical page and physical page is fully associative. This scheme decreases the capacity of mapping table significantly and provides excellent performance as smoothly as pure page-mapping scheme. The latter achieves the pure page-mapping FTL performance at the RAM cost of a block-mapping FTL while consuming lower energy, by hiding the address translation. The basic idea of this scheme is to create a separate access path to read/write the address mapping information to significantly hide the address-translation latency by incorporating a low energy-consuming solid-state memory device that stores the entire page mapping table.The buffer-cache of an SSD plays an essential role in bridging the speed gap between flash storage media and the host interface. While the existing SSD buffer management schemes are designed to improve SSD performance, they are often ineffective when serving the widespread bursts of I/O traffic in data-intensive workloads. To address this problem, this paper proposes a Proactive and Adaptive SSD buffer Scheme (PASS) to judiciously and actively flush dirty data in anticipation of traffic bursts by exploiting the light-traffic intervals, as well as the chip-level and channel-level parallelism inside SSD. The experimental results show that PASS significantly and consistently outperforms the state-of-the-art buffer schemes in both response time and endurance measures.SSDsim is event-driven, modularly structure, multi-tiered and open-source SSD simulator. It is capable of simulating most SSD hardware platforms, mainstream FTL schemes, allocation schemes, buffer management algorithms and request scheduling algorithms. The three tiered SSDsim design consists of the buffer module at the top, the FTL and allocation module in the middle, and the low-level hardware platform module at the bottom. By feeding block-level trace files and configuring the parameter files, the waiting time, processing time, response time of each request, total erasure count, buffer hit count and other detailed information can be obtained. To validate the accuracy of SSDsim, a real SSD hardware prototype has been implemented. The average response time obtained from SSDsim is very close to that obtained from the prototype, which indicates the high accuracy of SSDsim.更多还原