【作者】 张波；

【导师】 严晓浪；

【作者基本信息】 浙江大学 ， 电路与系统， 2012， 博士

【摘要】 根据国际半导体技术发展蓝图(ITRS),集成电路已经进入“后摩尔”(More than Moore)时代,集成电路制造的工艺尺寸不断减小,国际最先进工艺已经到达28nm以下。随着集成电路工艺尺寸到达纳米级别,集成电路制造工艺越趋复杂,制造工艺缺陷及设计缺陷对成品率的影响越来越大。同时集成电路制造的设计规则也越来越复杂,设计规则数目迅速增加,需要设计成千上万的不同测试结构来检测和分析制造工艺缺陷和各设计规则的成品率缺失。另一方面,随着制造工艺水平的提高,在生产线上制造芯片的费用不断上涨。多项目晶圆(Multi Project Wafer,简称MPW)就是将多个使用相同工艺的集成电路设计放在同一晶圆片上流片,制造完成后,每个设计可以得到数十片芯片样品,这一数量对于原型(Prototype)设计阶段的实验、测试已经足够。而该次制造费用就由所有参加MPW的项目按照芯片面积分摊,成本仅为单独进行原型制造成本的5%-10%,极大地降低了产品开发风险、培养集成电路设计人才的门槛和中小集成电路设计企业在起步时的门槛。如何设计更加合理的布局以减少晶圆切割时对多项目晶圆中芯片的损坏,提高多项目晶圆的成品率,也成为了现代集成电路行业研究的热点之一。本文围绕测试芯片设计及提高集成电路成品率展开了以下几方面研究：1.根据纳米级制造工艺特点以及对成品率数据分析需求,基于制造工艺的通用设计规则,完成了成品率测试所需的各类测试结构的参数化建模,为后续的成品率测试芯片自动化设计奠定了坚实的基础；2.针对测试芯片中测试结构的相似性特点,以及制造工艺设计规则中不同图层的相关性特点,创造性的提出并实现了版图生成器,并基于实验设计(DOE, Design of Experiment)的要求完成了各类测试结构的自动化生成；同时,针对传统Short Flow设计的测试芯片中测试结构直接连接到终端(PAD)的特点,完成对测试结构布局和布线的建模,并实现测试芯片的布局和布线自动化设计,提升了测试芯片设计效率；3.针对先进的可寻址测试芯片设计复杂、测试结构容量更大、对自动化设计要求更高的特点,提出一种模块化可扩展的设计方法,该方法能够极大地减少PAD数目以及传输门器件所占面积,可以实现对测试结构的精确的四端测量,测试结构尺寸和测试阵列规模都具有良好的可扩展性,同时能够发现纳米级集成电路制造工艺的多种缺陷；4.深入分析了切割对多项目晶圆造成的成品率缺失,提出了一种基于模拟退火(SA)算法的多项目晶圆布局规划方法,该方法充分考虑切割对芯片的损耗情况,利用模拟退火算法自动计算出最优布局结果,能够减小切割损耗,提高多项目晶圆的芯片成品率。更多还原

【Abstract】 According to report by International Technology Roadmap for Semiconductors (ITRS), semiconductor industry has entered the "More than Moore" era, and the continued shrinking of physical feature size of integrated circuit has reached the stage of under 28nm. When the technology dimension steps into nanometer scale, the process of manufacturing becomes much more complex and the expensive, while the process defect caused yield loss and the design-based yield loss is becoming the most significant source of yield loss. Meanwhile, the number of design rules is rapidly increased with every node of technology circle and thousands of unique test structures per layer are needed to achieve yield characterization and detect process defect.In the other hand, IC fabrication costs are turning into extremely expensive. Multi-Project Wafer (MPW) integrates onto microelectronics wafers a number of different integrated circuit designs from various teams including designs from private firms, students and researchers from universities. It makes sense to share mask and wafer resources to produce designs in low quantities, which is enough for experiments and testing in prototype step. The costs are shared by all the teams according to the chip area, which would be 5%-10% of the cost of individual. MPW can lower the development risk and the threshold for market entry and human resource training. To achieve a proper reticle floorplanning, which can reduce the dicing cost and yield loss, is becoming one of the research hot spots of IC design. Focusing on test chip design and yield improvement, this thesis starts the following research work:1. According the characteristics of nanometer scale manufacture technology and request of data analysis of yield improvement, based on generic design rules of fabrication, we finish the parameterization for each type of test structures. Be prepared for test chip design automation.2. Based on the similarity of test structures and relation of different layers in fabrication design rules, we create a layout generator, and finishe layout auto-generation for various types of test structures as the design of experiment (DOE) demands In short-flow test chip, test structures are connected to PAD directly. We finish the modeling of placement and routing, and realize the auto placement and routing for short-flow test chip, which provides an efficient method of test chip layout design. 3. Addressable test structure array with more complex circuit and layout design has large volume of test structures, which has a strict request for layout automation. We present a modular unit based method of scalable test structure array design. By combining the device-under-test (DUT) and the switching devices into a standard modular unit, this method not only implements the four-terminal measurement to ensure the accuracy of the testing, but also significantly reduces mask consumption of test chips. The experiment results demonstrated that the process window can be tracked with those arrays, which further proves the accuracy and effectiveness of the presented design.4. After deeply analysis of the yield loss of chips in MPW caused by dicing, we present a novel simulated-annealing based floorplanning for MPW, which takes chip damage caused by dicing into consideration. This floorplanning method can reduce the dicing loss and improve the chip yield of MPW.更多还原