【作者】 尹海丰；

【导师】 毛志刚；

【作者基本信息】 哈尔滨工业大学 ， 微电子学与固体电子学， 2009， 博士

【摘要】 锁相环广泛应用于数字系统的时钟产生器、无线通信领域的频率合成器和时钟/数据恢复电路。随着时钟频率的增加,数字系统对时钟信号的抖动性能提出了更严格的要求。锁相环如果在较宽的频率范围内实现输出低抖动信号,则可以应用于有不同频率要求的数字系统中,不必为每个专用集成电路设计独立的锁相环,节约了设计和验证的成本,本文研究了在宽输入/输出频率范围内实现低抖动锁相环的设计问题。通过对锁相环的工作原理、结构和电荷泵锁相环理论的分析,列举了影响锁相环总体性能的一些子模块以及系统设计的要求。分析了环路延迟对锁相环稳定性的影响,由于环路中的极点也将反馈信号进行了延迟,环路延迟也可以看作是一个额外极点的影响,影响环路稳定性的延迟量将表现出近似与带宽呈反比的关系,将延迟等价的极点引入开环传递函数使得我们在考虑环路延迟影响的情况下,仍然可以使用传统的s域分析方法。研究了电荷泵锁相环的噪声和抖动特性。通过对前人关于振荡器相位噪声模型的研究,在线性时变模型的基础上,探讨了振荡器的噪声,并考虑了较强噪声干扰情况下此模型的非线性问题。分析了锁相环中的噪声源,重点研究了热噪声、1/f噪声和应用环境中的数字开关噪声对输出信号噪声的影响,给定噪声强度和工艺条件,根据噪声模型和各模块噪声到输出相位噪声的传递函数可以计算出振荡器和锁相环输出信号噪声的功率谱,根据此功率谱也可以计算出输出信号抖动的大小。由于振荡器噪声到输出相位噪声传输的高通特性,在振荡器噪声占主导的情况下,输出信号频谱在频率偏移为环路带宽的频率处呈现出一个峰值,因此环路带宽应最大化以减小这个峰值从而更多的抑制振荡器的噪声,但是为了保持环路稳定性,此带宽与参考频率的比不能大于一定值,所以此类锁相环的低抖动设计原则就是要使环路带宽跟随参考频率变化,同时要保证环路稳定性。本文提出了自适应带宽的电荷泵锁相环的设计方法和新结构。传统固定带宽的电荷泵锁相环只能在一个工作状态下达到最优化的输出信号抖动性能,自适应带宽锁相环可以动态调整锁相环参数以达到在各个工作点输出低抖动信号,这些特性包括环路带宽跟随参考频率变化和固定的阻尼因子。本文提出的应用于时钟产生器的自适应带宽锁相环设计方法将锁相环等效成积分控制环路和成比例控制环路,研究了自适应带宽锁相环对这两个控制环路的要求,这两个呈比例项和积分项需要分别保持与参考频率和参考频率的平方呈比例,用此方法解释了前人基于自偏置技术的锁相环结构的不足,给出了改进方案。提出了一个宽频率范围的基于电流模自偏置技术的锁相环新结构,此结构采用电流控制振荡器,两条控制环路分别实现,直接由电流过冲实现呈比例项,实现此项的电荷泵电流与振荡器控制电流呈比例,而实现积分项电荷泵电流的比例因子受参考频率控制,从而达到了自适应带宽对这两个控制环路的要求。新结构解决了传统自偏置锁相环的环路稳定性受分频比限制以及电流模自偏置锁相环的环路稳定性受参考频率限制的问题,能够达到较宽的输入/输出频率范围和分频范围,而且保持了自偏置技术抗工艺、电源电压和温度变化的特性。给出了锁相环的设计和测试结果。完成了宽频率范围电流模自偏置锁相环的电路和版图设计,通过后仿真验证了其环路稳定性,达到了宽输入/输出频率和分频范围。另外,用90 nm全数字CMOS工艺实现了一个自偏置锁相环设计,验证本文低抖动设计原则,测试结果表明锁相环实现了低抖动输出。更多还原

【Abstract】 Phase-Locked Loops (PLLs) are widely used as clock generators for digital systems, frequency synthensisors for wireless communication and clock/data recovery circuits. As the clock frequency increasing, digital systems have strict requirements for clock signals’jitter performance. If a PLL could achieve low jitter output signal in a wide frequency range, it can be used in digital systems which have different frequency requirement. Therefore, it is not necessary to design special PLLs for each ASIC and the low design and verification cost is achieved. This research focuses on designing a low jitter PLL in a wide input/output frequency range.The PLL sub-blocks and system design requirements that influence the PLL general performances are enumerated, through analyzing the PLL operating principle, structure and charge pump PLL theory. The loop delay’s influence on the loop stability is analyzed. Since the pole delays the feedback signal, the loop delay can also be regard as a pole. The delay value which affects the loop stability is reversely proportional to the loop bandwidth approximately. The open loop transfer function with a delay equivalent pole makes it possible to use the classic s domain analysis method, considering the delay’s influence.The charge pump PLL noise and jitter properties are studied. Through previous research of oscillator phase noise models, the oscillator noise is analyzed based on the linear time variant model, considering the nonlinear property under strong noise environments. Noise sources in PLLs are studied, with emphasis on the thermal noise, the 1/f noise, the digital switching noise in application environments and their influence to the output signal noise. Given the noise power and the technology condition, the oscillator and PLL output signals’noise power spectra can be computed according to noise models and noise transfer functions. Under the condition of a dominant oscillator noise, a peak value appears in the power spectra with an offset frequency of the loop bandwidth because of the high pass property of the oscillator noise. Therefore, the loop bandwidth should be maximized to lower the peak value and reject more noise in oscillators. However, the ratio of the loop bandwidth and the reference frequency can not exceed a certain value. The low jitter design principles for this kind of PLLs are that the loop bandwidth tracks the reference frequency and the loop stability is ensured at the same time.The adaptive bandwidth PLL design method and a new PLL structure are presented. Classic charge pump PLLs can only achieve the most optimized output jitter performance in a perticular operating condition. Adaptive bandwidth PLLs can dynamicly adjust PLL parameters to achieve a low jitter output signal under any operating conditions. These charactors include a bandwidth tracking the reference frequency and a fixed damping factor. The presented adaptive bandwidth PLL design method for clock generators regards the PLL as a proportional and an integral control loops. The adaptive bandwidth PLL’s reqirements to these two loops are researched. The proportional and the integral control loops should be proportional to the reference frequency and the square of the reference frequency separately. Furthermore, the previous self-biased PLL structures’drawbacks are explained using this method and improved structures are proposed. A new current mode self-biased PLL structure which has a wide frequency range is presented. A current controlled oscillator is used and the two control loops are implemented independently. The proportional loop is implemented by the current over rush derectly and the charge pump current is proportional to the oscillator control current. However, the proportional factor of the integral loop charge pump is controlled by the reference frequency. The PLL new structure resolves problems that the classic self-biased PLL’s loop stability is restricted by the frequency division ratio and the current mode self-biased PLL’s loop stability is restricted by the reference frequency. A wide input/output frequency range and frequency division range could be achieved and the independence of process, power and temperature (PVT) is kept.The PLL design and measurement results are presented. The wide frequency range current mode self-biased PLL’s circuits and layout designs are finished and the loop stability is verified through post simulations. A wide input/output frequency and frequency division range are achieved. Furthermore, a self-biased PLL is designed and fabricated in a 90 nm digital CMOS process and low jitter design principles are verified. Measurement shows that the PLL achieves low jitter ouput.更多还原