【作者】 孙强；

【导师】 马光胜；

【作者基本信息】 哈尔滨工程大学 ， 计算机应用技术， 2009， 博士

【摘要】 半导体技术的飞速发展及VLSI集成度和时钟频率的不断提高，使得电路的可测性和功耗问题逐渐成为VLSI设计首要考虑的因素。当前许多研究表明高层次设计能够最大程度地实现可测性和功耗的优化，这是因为高层次设计对具体实现的依赖性很小，对算法和架构的选择自由度高，而算法和架构对最终硬件实现的可测性和功耗影响显著，能够使最终电路在可测性和功耗方面产生良好的优化效果。因此，高层次测试综合和高层次低功耗综合设计技术引起了学术界的广泛关注。本文首先对当前高层次综合及可测性和低功耗设计技术进行了综述，在此基础上对高层次测试综合和高层次低功耗综合进行深入研究，通过将高层次综合与可测性设计和低功耗设计相结合，来解决当前集成电路发展所面临的问题。本文主要工作如下：1)提出一种基于加权相容图的可测性寄存器分配方法，给出了一个基于可测性高层次综合准则的相容图边的权值公式，并运用改进的加权团划分算法对加权相容图进行处理，在寄存器分配过程同时考虑可测性高层次综合的四个准则，达到了设计电路可测性改善的目标。实验结果表明该方法在可测性方面的有效性。2)通过对控制流密集型电路高层次功耗优化问题的分析和研究，提出一种面向控制流密集型电路的高层次低功耗综合设计方法。该方法首先对控制数据流图中的控制节点进行调度，在控制节点和其目标传递扇入之间建立控制边，关闭不必要的操作节点，实现功耗的优化；然后运用基于多电压的功耗优化调度方法对调度完的控制数据流图进行再调度，最终实现设计电路功耗的最大优化。该方法不但能够很好地解决控制流密集型电路的功耗优化问题，而且对于数据流密集型电路也同样适用。实验结果表明该方法具有较好的功耗优化能力和较低的时间复杂度。3)通过对当前高层次测试综合和高层次低功耗综合技术的深入研究，将可测性设计和低功耗设计相结合，提出一种基于遗传算法的高层次可测性和低功耗综合方法。该方法在时间和面积约束下，通过高层次调度和模块分配，对可测性和低功耗问题进行研究。利用“加权和”形式求得综合反映各个子目标要求的单一适应度函数，将多目标优化问题转化为可利用单目标进化算法求解的等效问题。文中给出了一种可以同时进行高层次调度和模块分配的遗传算法染色体编码方式，并设计了基于数据依赖的单点杂交算子和基于控制步约束的变异算子，避免了进化过程中不可行解的产生。实验结果表明该方法在可测性改善和功耗优化方面的有效性。更多还原

【Abstract】 The testability and power dissipation of circuit have become the principal problems in the design of very large scale integration (VLSI) due to the rapid development of semiconductor technique and the constant improvement of integration level and clock frequency of VLSI. Nowadays, many studies show that high-level design can maximally optimize testability and power dissipation as a result of its little dependence on implementation and high freedom of algorithm and architecture. In addition, algorithm and architecture have a remarkable effect on hardware testability and power dissipation, which can make satisfying optimal effects on testability and power dissipation of final circuit. Therefore, high-level test synthesis and high-level low power synthesis draw wide attention of academic world. This dissertation provides an up-to-date review of high-level synthesis (HLS), testability and low power design, on the basis of which a deep research is carried out on high-level test synthesis and high-level low power synthesis. Thus, the problems currently facing the development of integrated circuit can be solved through the combination of HLS, testability and low power. The major contributions of this dissertation are as follow:1) A register allocation method for testability is proposed on the basis of weighted compatibility graph. A weighted formula of compatibility graph edge based on the rules of high-level synthesis for testability is provided, and an improved weighted clique partition algorithm is used to deal with this weighted compatibility graph. Thereby, four rules for testability can be considered simultaneously in the procedure of register allocation and the goal of improving circuit testability is achieved. Experimental results show the effectiveness of this method for testability.2) A high-level low power synthesis method for control flow intensive design is proposed based on the analysis and the study of high-level power optimization of control flow intensive design. The operation procedure of this method is as follows: first schedule the control nodes in control data flow graph, then establish control edges between control nodes and the target transitive fanins, shut down unnecessary operate notes to save power dissipation, next reschedule the scheduled control data flow graph by using power dissipation optimization scheduling method based on multiple voltages to maximize optimization of circuit power dissipation. This method can not only perfectly satisfy the needs of power dissipation optimization in control flow intensive design, but also be suitable for data flow intensive design. Experimental results have shown its high power dissipation optimization quality and low algorithm time complexity.3) After the deep study of high-level test synthesis and high-level low power synthesis, a high-level testability and low power synthesis method based on genetic algorithm is proposed, which combines testability design and low power design. Under time and area constraint, this method studies the testability and low power by way of high-level scheduling and module allocating. Through weighted form, a single fitness function is obtained, which can reflect the requirements of each subobjective. Thereby, the multi-objective optimization problem can be converted to a single objective problem. Besides, a chromosome coding of genetic algorithm is proposed that can be used for high-level scheduling and module allocating simultaneously, and one point crossover operator based on data dependence and mutation operator based on control step constraint are designed, hence, avoiding the generation of infeasible solutions. The efficiency of testability improvement and power dissipation optimization of this method is demonstrated by experimental results.更多还原