【作者】 罗小蓉；

【导师】 李肇基；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 博士

【摘要】 SOI（Silicon On Insulator）高压集成电路（High Voltage Integrated Circuit,HVIC）因其具有高速、低功耗、抗辐照以及易于隔离等优点而得以广泛应用。作为SOIHVIC的核心器件,SOI横向高压器件较低的纵向击穿电压限制其在高压功率集成电路中的应用。为此,国内外众多学者提出了一系列新结构以提高SOI横向高压器件的纵向耐压。但迄今为止,SOI横向高压器件均采用SiO₂作为埋层,且实用SOI器件击穿电压不超过600V;同时,就SOI横向器件的电场分布和耐压解析模型而言,现有的模型仅针对具有均匀厚度埋氧层和均匀厚度漂移区的SOI器件建立;而且,没有一个统一的理论来指导SOI横向高压器件的纵向耐压设计。本文围绕SOI横向高压器件的耐压问题,从耐压理论、器件结构和耐压解析模型几方面进行研究。基于SOI器件介质层电场临界化的思想,提出介质场增强ENDIF（ENhanced DIelectric layer Field）理论,在ENDIF理论指导下,提出三类SOI横向高压器件新结构,建立相应的耐压解析模型,并进行实验。1、ENDIF理论对现有典型横向SOI高压器件的纵向耐压机理统一化。ENDIF理论的思想是通过增强埋层电场而提高SOI横向器件的纵向耐压。ENDIF理论给出了增强埋层电场的三种途径:采用低k（相对介电常数）介质埋层、薄SOI层和在漂移区/埋层界面引入电荷,并获得了一维近似下埋层电场和器件耐压的解析式。ENDIF理论可对现有典型SOI横向高压器件的纵向耐压机理统一化,它突破了传统SOI横向器件纵向耐压的理论极限,是优化设计SOI横向高压器件纵向耐压的普适理论。2、基于ENDIF理论,提出以下三类SOI横向高压器件新结构,并进行理论和实验研究。（1）首次提出低k型介质埋层SOI高压器件及其耐压解析模型低k型介质埋层SOI高压器件包括低k介质埋层SOI高压器件、变k介质埋层SOI高压器件和低k介质埋层PSOI（Partial SOI）高压器件。该类器件首次将低介电系数且高临界击穿电场的介质引入埋层或部分埋层,利用低k介质增强埋层电场、变k介质调制埋层和漂移区电场而提高器件耐压。通过求解二维Poisson方程,并考虑变k介质对埋层和漂移区电场的调制作用,建立了变k介质埋层SOI器件的耐压模型,由此获得RESURF判据。此模型和RESURF判据适用于变厚度埋层SOI器件和均匀介质埋层SOI器件,是变介质埋层SOI器件（包括变k和变厚度介质埋层SOI器件）和均匀介质埋层SOI器件的统一耐压模型。借助解析模型和二维器件仿真软件MEDICI研究了器件电场分布和击穿电压与结构参数之间的关系。结果表明,变k介质埋层SOI高压器件的埋层电场和器件耐压可比常规SOI器件提高1倍和83%,当源端埋层为高热导率的Si₃N₄而不是SiO₂时,埋层电场和器件耐压分别提高73%和58%,且器件最高温度降低51%。解析结果和仿真结果吻合较好。（2）提出并成功研制电荷型介质场增强SOI高压器件本文提出的电荷型介质场增强SOI高压器件包括（a）双面电荷槽SOI高压器件和电荷槽PSOI高压器件,其在埋氧层的一侧或两侧形成介质槽。根据ENDIF理论,槽内束缚的电荷将增强埋层电场,进而提高器件耐压。电荷槽PSOI高压器件在提高耐压的基础上还能降低自热效应;（b）复合埋层SOI高压器件,其埋层由两层氧化物及其间多晶硅构成。该器件不仅利用两层埋氧承受耐压,而且多晶硅下界面的电荷增强第二埋氧层的电场,因而器件耐压提高。本文开发了基于SDB（Silicon Direct Bonding）技术的非平面埋氧层SOI材料的制备工艺,并研制出730V的双面电荷槽SOI LDMOS和760V的复合埋层SOI器件,前者埋层电场从常规结构的低于120V/μm提高到300V/μm,后者第二埋氧层电场增至400V/μm以上。（3）提出薄硅层阶梯漂移区SOI高压器件并建立其耐压解析模型。该器件的漂移区厚度从源到漏阶梯增加。其原理是:在阶梯处引入新的电场峰,新电场峰调制漂移区电场并增强埋层电场,从而提高器件耐压。通过求解Poisson方程,建立阶梯漂移区SOI器件耐压解析模型。借助解析模型和数值仿真,研究了器件结构参数对电场分布和击穿电压的影响。结果表明,对t_I=3μm,t_S=0.5μm的2阶梯SOI器件,耐压比常规SOI结构提高1倍,且保持较低的导通电阻。仿真结果证实了解析模型的正确性。更多还原

【Abstract】 SOI HVIC（High Voltage Integrated Circuit） is widely applied due to the advantages such as high speed, low power dissipation, perfect irradiation hardness and superior isolation. SOI lateral high voltage devices are the key devices in SOI HVIC, of which the low vertical breakdown voltage limits the application in high voltage and power integrated circuit. A lot of novel structures have been proposed to enhance the vertical breakdown voltage of SOI lateral high voltage device. However, up to now, silicon dioxide is used as the buried layer and the breakdown voltage of the applied SOI devices is less than 600V. At the same time, as for the analytical models for the electric field distribution and breakdown voltage of SOI lateral devices, the existing analytical models are presented only for SOI device with the constant thickness buried oxide layer and the constant thickness drift region. Furthermore, no unified principle can be used to design SOI lateral high voltage device to enhance the vertical breakdown voltage.In this thesis, addressed the breakdown voltage problem of SOI lateral high voltage device, the breakdown theory, the new device structures and breakdown analytical models are researched. Based on the concept of the critical field approaching for the dielectric field, ENDIF（ENhanced Dielectric layer Field） principle is presented, by which three kinds of the novel SOI lateral high voltage device structures are proposed. The analytical models are presented and some experiment results are obtained for these novel device.1. The vertical breakdown mechanisms of the typical SOI lateral high voltage devices are unified by ENDIF principle.The concept of ENDIF principle is that the vertical breakdown voltage is improved by enhancing the electric field in the buried layer. Three methods for enhancing the electric field in the buried layer are given, including using the low k dielectric buried layer, using thin SOI film and implementing the charges on the interface between SOI layer and buried layer. The expressions for the electric field in the buried layer and the breakdown voltage are obtained under the one-dimension approximation. The vertical breakdown mechanisms for the existing typical SOI lateral high voltage devices are unified by ENDIF. ENDIF principle breaks through the theoretic limit of the vertical breakdown voltage for the conventional SOI lateral devices. It is a general principle to design the vertical breakdown voltage for SOI lateral high voltage devices.2. Based on the ENDIF principle, the following three kinds of novel structures are proposed, for which theories and experiments are carried out..（1） The novel structure and its breakdown analytical model for SOI high voltage device with low k dielectric buried layer are proposed.The kind of the high voltage device includes SOI device with the low-k dielectric buried layer, SOI device with the variable-k dielectric buried layer and Partial SOI device with the low-k dielectric buried layer, in which the low-k dielectric with the high critical electric field is firstly used as the buried layer or partial buried layer. The electric field in the buried layer is enhanced and the ones in SOI layer and buried layer are modulated by the low-k and variable-k buried layer, resulting in the enhancement of the breakdown voltage. By solving 2-D Poisson equation, taking into consideration the modulation effects, the breakdown analytical model for SOI device with the variable-k dielectric buried layer is presented, from which the RESURF criterion is derived. The model and RESURF criterion can also been applied to SOI devices with the variable-thickness buried layer and with the uniform dielectric buried layer. Therefore, the model is a unified model for SOI devices with the variable dielectric buried layer （including the variable-k and variable-thickness dielectric buried layer） and with the uniform dielectric buried layer. The dependences of the electric field distributions and the breakdown voltage on the structure parameters are discussed by the analytical model and the numerical simulation. The results show the electric field of the buried layer and breakdown voltage for SOI device with the variable-k dielectric buried layer are enhanced by 100% and 83% compared with those of the conventional SOI, respectively. For SOI device with the variable-k dielectric buried layer, of which Si₃N₄ instead of SiO₂ is the buried layer at source side, the electric field in the buried layer and breakdown voltage are enhanced by 73% and 58%, respectively, moreover, the maximal temperature is lowered 51%. The analytical results are in good agreement with those of numerical simulations.（2） The novel structures of SOI high voltage device with charge mode and their experimental results are reported. In this thesis, the proposed SOI high voltage device structures with charge mode include （a）SOI high voltage device with the double-side charge trench and PSOI device with the charge trench, in which the dielectric trenches are formed on one or two interfaces of buried oxide layer. The charges located in the trenches increase the electric field in buried layer and modulate the electric field in SOI layer, therefore, the breakdown voltage is enhanced. PSOI device with the charge trench can not only enhance the breakdown voltage, but also lower the self-heating effect; （b）SOI device with the composite buried layer, in which the composite buried layer is made of two oxide layers and polysilicon between them. Its breakdown voltage is shared by two layers buried oxide, furthermore, the charges on the bottom interface of the polysilicon layer enhance the electric field in the second buried layer, so breakdown voltage is enhanced. The fabrication process of SOI material with non-planar buried layer is developed based on SDB（Silicon Direct Bonding） technology. 730V SOI LDMOS with the double-side charge trench and 760V SOI device with the composite buried layer are obtained for the first time. The electric field in the buried oxide layer increases from below 120V/μm of the conventional SOI to over 300V/μm for the former and over 400V/μm for the second buried layer for the latter.（3） The new structure and its analytical model for the thin film SOI high voltage device with step drift region are proposed.The new structure and its breakdown voltage analytical model are proposed. The new electric field peaks are generated at the steps, which modulates the electric field in SOI layer and enhances that of the buried layer, resulting in the enhancement of the breakdown voltage. A breakdown analytical model for the proposed SOI high voltage device is proposed by solving Poisson equation. The effects of the device structure parameters on the electric field distributions and the breakdown voltage are discussed by the analytical model and the numerical simulation. The results show the breakdown voltage for the thin film SOI device with two steps is as high as twice of the conventional SOI device at t_I=3μm , t_S=0.5μm , maintaining the low specificon-resistance. Numerical simulations support the analytical model.更多还原