【作者】 史晓锋；

【导师】 陈咏恩；

【作者基本信息】 同济大学 ， 控制理论与控制工程， 2007， 博士

【摘要】 我国已经将DVB-C标准确定为有线数字电视的国家标准，随着模拟电视向数字高清晰度电视逐渐过渡，对高性能有线数字电视解调芯片的需求持续增长，其VLSI实现已经成为国内外学术界和工业界的一个热点问题，具有重要的理论和实践价值。由于信号在电缆中传输，DVB-C选择适合高信噪比环境的QAM调制方式，其基带接收芯片是一种宽带的QAM解调器。QAM调制解调已经在较低数据速率的电话信道中得到成熟应用，目前的研究集中在高数据率的宽带通信领域，取得了丰富的成果，但同时也面临大量的技术难点有待解决。有线电视网络是典型的广播网络，发射机无法为接入用户提供训练序列，发送内容中也没有已知信息，“盲接收”思想成为本课题的研究重点和难点。另外，随着集成电路技术的飞速发展，芯片的规模不断扩大，设计的复杂度不断提高，验证成为芯片设计中最困难、最具有挑战性的问题之一，是影响芯片开发周期的关键因素。本文以DVB-C基带芯片的算法和VLSI设计为研究重点，但不局限于这一具体设计。通过对QAM解调中的盲接收、同步和均衡等技术的研究，结合具体芯片的验证工作，解决QAM解调芯片设计与验证中的共性问题，研究成果可以应用在HDTV、Cable modem、卫星和数字微波通信等基于QAM的宽带通信领域，对通信类基带芯片的设计和实现有相应的指导意义和较高的参考价值。本论文的主要内容包括：1，在研究DVB-C标准的基础上，将盲接收思想应用到系统设计中，讨论盲接收的算法选择和当前面临的主要问题，对系统设计阶段，性能与可行性之间要达到的折衷做出分析。2，详细分析了采用Gardner算法的时钟同步环路的性能，指出提高性能的途径。讨论插值器的设计方法，重点分析拉格朗日插值的性能。给出时钟同步环路整体的性能仿真结果。3，选择载波同步环路在数据链路上位置，研究基于判决的鉴相算法，以及在此基础上为扩大频偏捕获范围，缩短捕获时间所做出的算法改进，给出性能比较的仿真结果。简单介绍采用CORDIC算法的直接数字频率合成技术。4，简单回顾基于随机梯度迭代的盲均衡算法，重点讨论独立于载波的常模数算法。从均衡器是否包含反馈以及反馈的方式、采用直接型或者倒置型滤波器结构、采用符号间隔还是分数间隔这三个方面，分析不同结构均衡器的特点。给出采用不同算法和结构均衡器的性能仿真结果。5，研究在混合信号电路(AGC和ADC)设计过程中面临的主要问题和解决方法。提出芯片中固定系数FIR滤波器和均衡器等关键模块的优化实现方案。设计结果表明这些优化保证了解调器的整体性能指标。6，研究基于SystemC的定点仿真技术和基于参考模型的功能验证，提出时序精度层次的参考模型。对基于FPGA的原型验证系统的组成、流程和一些基本验证准则进行了讨论。以DVB-C基带芯片为实例，针对基带芯片验证中的难点提出相应策略。更多还原

【Abstract】 DVB-C has been the national standard of digital Cable TV in our country. With stepping into HDTV era from analog TV, the increasingly requirement of demodulator chips with high performance is evident. The VLSI design of demodulator chip has become one of the focuses of academic and industrial research.Since coaxial-cable is the transmission media, Quadrature Amplitude Modulation, which works well in the invirenment of high signal to noise ratio, is used in DVB-C standard, and DVB-C baseband chip is subsequently a wide-band QAM demodulator. QAM modem has been widely used in telephone channel, and researches now focus on the area of wide-band communication with high data rate. Although there are many productions in these years, we also face to a number of unresolved technology difficulties.As Cable TV net is a typical broadcast net, transmitters can not provide training sequence to users that probably connect in momentarily, and there is no information with previous knowledge in transmission content. So blind receiving is one of the key problems of this dissertation. With the great progress of IC technology, scale of chips and complexity of design are keeping increase. Verification becomes one of the most difficult and challenging problem in IC design, and becomes the key factor in design periods.This dissertation focuses on DVB-C baseband chip design, but not limited on it. Common problems of design and verification in QAM demodulators are solved by doing research on synchronization, equalization and other key techniques in QAM demodulation and large amount of verification work. The productions can be implemented in HDTV, cable modem, satellite, micro wave communication et al that based on QAM, and give direction and reference to communication base-band chip design. The main contribution of this dissertation can be concluded as following:1, Based on studies of DVB-C standard, the idea of blind receiver is applied in system design, discusses algorithm choices and unresolved problems in current research, makes some analysis with trade off between performance and realization in stage of system design.2, Timing recovery loop with Gardner algorithm is discussed in detail, and method of improving performance is given. Some design methods of interpolation filters are proposed and performance of Lagrange interpolation is analyzed.3, By doing analysis on phase detect algorithm based on decision direct, some improvement of extending acquisition range and reducing acquisition time is proposed, simulation results are given. There is also an introduction of direct digital frequency synthesis based on CORDIC algorithm.4, A review of blind equalization algorithm based on stochastic gradient recursion is proposed, and constant modulus algorithm that independent of carrier is mainly discussed. Comparison between linear and decision feedback, direct form and transpose form, symbol spaced and fractionally spaced equalizers is discussed and simulation results are given.5, Problems and solutions in mixed signal design are proposed. According to all-digital implementation scheme, this work proposes various optimization techniques to improve the performance of key modules, such as anti-aliasing filter, match filter and equalizer. Design results show that current optimizations guarantee the performance of the demodulator.6, By learning fixed point simulation and reference model techniques based on SystemC, this work proposes a reference model of cycle accurate level. Structure, flow and criteria of FPGA prototype verification system are discussed. Some specialties for verification of baseband chip are proposed, too.更多还原