【作者】 王超；

【导师】 张义门；

【作者基本信息】 西安电子科技大学 ， 微电子学与固体电子学， 2008， 博士

【摘要】 半绝缘碳化硅(SiC)材料对于SiC器件的制作和性能具有非常重要的意义,特别是对功率器件、深亚微米器件和微波功率器件更是如此。半绝缘材料既可以做器件的衬底,又可以作为器件间的隔离。更重要的是,无论从电特性还是导热特性来讲,半绝缘SiC都是在光电和微波功率器件中具有重大应用前景的另一种宽禁带半导体材料GaN最好的衬底材料。由于对高阻材料的测量分析非常困难,因此关于钒掺杂生长半绝缘SiC的补偿机理和材料特性还没有一套系统的表征测试方案。离子注入是唯一适于SiC的选择性区域掺杂方法,目前国际上对钒离子注入制备半绝缘SiC的研究很少,而国内在这方面的研究仍属空白。SiC材料的离子注入本身就存在许多问题,如注入缺陷的消除、退火工艺的优化、杂质激活率的提高等问题都有待于研究解决。此外,关于钒作为深受主杂质在4H-SiC中的能级位置,国际上仍存在较大争议。本文对钒离子注入制备半绝缘4H-SiC的机理、方法和特性进行了系统的理论和实验研究,对钒掺杂生长的半绝缘6H-SiC单晶体材料的补偿机理和材料特性进行了表征测试,主要的研究成果如下:(1)深入研究了几种不同的半绝缘SiC材料的形成机理和制备方法,对钒掺杂p型和n型SiC形成半绝缘材料的补偿机理和物理特性进行了详细的分析研究。通过研究离子注入理论和工艺特性,采用蒙特卡罗(Monte Carlo)方法,借助Trim模拟软件对钒离子注入SiC的分布进行了统计计算,计算模拟了不同注入能量下钒注入SiC的平均投影射程、标准偏差以及浓度分布。提出了钒离子注入制备半绝缘SiC的工艺流程及测试方案,包括注入工艺参数(能量和剂量)、退火条件和测试结构的设计等。(2)研究了退火条件对钒注入SiC材料特性的影响,发现1650℃的退火温度对注入引起的晶格损伤起到了很好的修复作用,退火后样品的结晶品质-最小产额比χmin(10.2%)接近初始样品的结晶品质χmin(8.6%)。经过高温退火,钒在SiC中的再扩散也不明显,钒在p型SiC中较在n型SiC中更为稳定。采用一种台面结构对样品进行I-V测试,发现钒注入层电阻率与SiC的初始导电类型关系很大,且随退火温度的升高而增加。经过1650℃退火后,常温下钒注入p型和n型4H-SiC半绝缘层的电阻率分别为1.6×1010 ?·cm和7.6×106 ?·cm。采用TLM结构对表面欧姆接触比电阻进行测量,发现接触电阻对半绝缘层的电学测试影响较小。对Ni基金属n型SiC的欧姆接触形成机理进行了研究,发现合金化后在金属层下面形成大量的碳空位(VC),起到浅能级杂质的作用,增加了自由载流子浓度,从而导致比接触电阻的降低。合金化退火过程中,Al-Ti金属与SiC反应形成的三元合金Ti3SiC2是p型SiC欧姆接触的主要原因。(3)研究了高温退火SiC表面形貌的影响。目前关于离子注入退火后SiC表面出现犁状沟槽缺陷的形成机制的理论和实验研究还是空白。通过对离子注入及退火前后SiC表面形貌和组分进行定性、定量分析,发现离子注入并不会导致表面粗糙,表面沟槽的形成是由于退火导致了SiC表面Si的析出,并伴随着少量的SiO2再沉积到样品表面所形成的,从理论上提出了沟槽缺陷的形成机制。设计了光刻胶碳化形成C膜覆盖层的退火保护工艺,并使用了内壁涂有多晶SiC粉的高纯石墨坩埚作为退火保护,研究表明该方法可以有效保护SiC表面承受1650℃的退火温度。(4)在借助钒离子注入成功制备了半绝缘4H-SiC的基础上,选择了精确有效的实验方法,通过对钒注入SiC样品分别进行变温电阻、低温光致发光和深能级瞬态谱测试分析,发现杂质钒在4H-SiC禁带中会形成两个深受主能级,分别位于导带下~0.8 eV和1.0~1.1 eV处,其电子俘获截面σn分别为7.0×1016 cm2和6.0×1016 cm2。这个发现可以很好地解释钒掺杂n型SiC形成的半绝缘层电阻率(106 ?·cm)比钒掺杂p型SiC的电阻率(1010~1012 ?·cm)低4~6个数量级这一现象。(5)提出了一套系统的钒掺杂生长半绝缘6H-SiC的表征测试方法,对半绝缘材料的补偿机理、结晶质量和晶片特性进行了研究。通过对SiC中的主要杂质以及钒在SiC中的电荷态进行测量分析,提出了掺钒生长半绝缘SiC的补偿机理,即掺入的钒在SiC中形成深受主杂质能级,通过束缚浅施主杂质能级上的自由电子,减小了自由载流子浓度,得到具有半绝缘特性的高阻材料。研究了钒作为深受主杂质在6H-SiC中的能级位置,发现其位于导带下0.62 eV处。借助拉曼光谱和X射线衍射对SiC的结晶质量进行研究,发现晶圆大部分区域结晶质量较好,边缘部分区域存在15R-SiC和6H-SiC多晶型共存。采用电阻mapping和光致发光mapping技术对晶圆进行测量,结果表明晶圆中钒掺杂浓度及电阻分布比较均匀,从中心区域到边缘区域,电阻率呈现环形等高线分布并逐渐递减,最大误差为11.7%。更多还原

【Abstract】 Semi-insulating silicon carbide (SiC) can be used for many applications related to high power device, deep submicron device, and microwave power device technology. One example is the need for semi-insulating substrates for high-power, high-frequency devices based on SiC and GaN because of their low dielectric losses in the GHz range and the high thermal conductivity. In addition, semi-insulating regions can also be applied for devices isolation or junction termination which is very important for improving the performances of devices. Due to the difficulty in the measurements of high resistance materials, it is necessary to systematically develop a series of test and characterization methods for the compensation mechanism and characteristics of semi-insulating SiC single crystal grown with the doping of vanadium. Ion implantation is a unique planar selective local doping technique available for making SiC devices. At present, there are few reports on the formation and characterization of semi-insulating SiC by vanadium ion-implantation. There are many difficulties and problems in the technique and process of ion-implantation of SiC material, such as the recovering of damage after implantation and annealing, the optimizing of annealing process, and the increasing of ions activation rate. At present, there are still diversities for the determination of the location of vanadium acceptor level in 4H-SiC. In this paper, the compensation mechanism, technology, and characteristics of the formation of semi-insulating SiC doped with vanadium are studied theoretically and experimentally. The main studies and contributions of this dissertation are as follows.(1) The fabrication and characteristics of semi-insulating SiC materials formed by several different methods are studied comprehensively. Detailed investigation of the compensation mechanism and physical properties of semi-insulating SiC doped with the vanadium in p- and n-type SiC are presented. From the analysis of theory and technique character of ion-implantation, the ion implantation range, location of peak concentration and longitudinal straggling of vanadium are calculated with the Monte Carlo simulator TRIM. The process flow of the formation of semi-insulating SiC by vanadium ion-implantation is proposed, including the determination of implantation energy and dose, annealing conditions, and mesa structure for measurements.(2) The characteristics of vanadium-implanted SiC materials in different annealing conditions are investigated. The annealing temperature of 1650℃is efficient for the recovering of damage caused by implantation. The minimum yieldχmin (10.2%) of the SiC material after annealing is closed to that of the initial material (8.6%). Significant impurity redistribution is not observed after 1650℃annealing for vanadium implanted both p- and n-type SiC. Vanadium in p-type SiC samples is relatively stable compared to in n-type samples during high temperature annealing. The test patterns on semi-insulating 4H-SiC samples were processed into mesa structure and resistivity measurements have been made. The resistivities of V-implanted layers are strongly dependent on the conduction type of initial 4H-SiC samples, and they are about 1.6×1010 ?·cm and 7.6×106 ?·cm for p- and n-type samples at room temperature, respectively. The specific contact resistance of ohmic contacts to 4H-SiC sample is investigated using linear transmission line method (TLM) structures. Comparing with the high resistivity of vanadium implanted layer (106~1010 ?·cm), the contact resistance can be neglected during current-voltage measurements. The physical mechanism in forming Nickel based ohmic contacts to n-type SiC is discussed. High temperature metallization annealing provides the enough C vacancies (VC), acting as donors, which contributes to the formation of ohmic contact. The physical mechanism in forming Al-Ti based ohmic contacts to p-type SiC is studied. It is thought that the formation of ternary Ti3SiC2 alloy during the metallization annealing is the main reason to play such an important role in converting the contact from Schottky to ohmic.(3) The surface morphology of vanadium-implanted 4H-SiC before and after annealing is investigated. At present, there are not theoretical and experimental reports on the mechanism of furrow defects on SiC surface after high-temperature annealing. From qualitative and quantitative analysis, it is found that the surface roughness is due to evaporation and re-deposition of Si species on the surface during annealing. A model is proposed to explain the observed surface roughness. The spin-coated photo-resist can be converted to graphite cap by thermal treatment. The graphite cap and high-purity crucible coated by poly-SiC is designed as the protection of SiC material during post-implantation annealing. Results show that carbon-capped 4H-SiC has a considerably lower surface roughness than surfaces annealed without the protective cap after 1650℃annealing.(4) Based on the fabrication of semi-insulating SiC layers by vanadium-implanted n-type 4H-SiC, the location of vanadium acceptor level in 4H-SiC band-gap is investigated by using temperature dependent resistance, low temperature photoluminescence (PL), and deep level transient spectroscopy (DLTS) measurements. Two acceptor levels of vanadium at EC-0.8 and EC-(1.0~1.1) eV with the electron capture cross section of 7.0×10-16 cm2 and 6.0×10-16 cm2 are obtained, respectively. This result can be used to explain the difference of resistivity between vanadium implanted p- and n-type SiC.(5) A standard test method for the compensation mechanism and characterization of semi-insulating 6H-SiC single crystal grown by vanadium doping is presented. As nitrogen is the principal shallow donor impurity in SiC by secondary ion mass spectroscopy (SIMS) measurements, semi-insulating properties in SiC are achieved by compensating nitrogen donor with the vanadium deep acceptor level. The presence of different vanadium charge states V3+ and V4+ is detected by electron paramagnetic resonance (EPR) and optical absorption measurements, which coincides with the results obtained by SIMS measurements. Both optical absorption and low temperature PL measurements reveal that the vanadium acceptor level is located at 0.62 eV below the conduction band in 6H-SiC. The main area of the wafer exhibits a good crystal quality by micro-Raman spectroscopy and X-ray diffraction (XRD) analysis. However, the polytype coexistence of 15R-SiC and 6H-SiC is observed in some parts of the periphery of the wafer. The resistivity and PL mapping measurements reveal a good homogeneity of electrical properties and vanadium doping concentration in the main area of the wafer. While the circular-shape resistivity distribution is observed with higher resistivity in the center and lower resistivity in the periphery of the wafer, and the maximum error of resistivity is 11.7%.更多还原