【作者】 李宇飞；

【导师】 谷大武；

【作者基本信息】 上海交通大学 ， 计算机系统结构， 2007， 博士

【摘要】 移动计算和数字多媒体的应用成为后PC时代的趋势已经是一个不争的事实,数字集成电路不断向专用化发展。面对大规模的数据量、计算量的需求,应用工程师发现各种处理器的功耗无法满足他们的设计要求,漫长的开发周期与设计收敛并快速上市成为一对无法调和的矛盾。为了解决这一问题,在低功耗设计领域,研究人员对门控时钟展开了大量的研究,它的基本思想是:通过减少数字电路的无效翻转次数来实现动态功耗减少的目的。在具体的实现上,当前主流的方式集中在电路级,通过对数字电路的逻辑进行分析,自动化的插入门控逻辑进行优化。此外,由于芯片规模和功耗的不断增加,带来测试的复杂度的增加,芯片在测试过程中损坏的风险大大增加。高强度的测试电流和过热往往导致在测试过程中对正常的芯片产生永久性破坏。此外,在供电回路的电源和地之间高密度的电流变化产生的噪声干扰到电路的正常工作,这导致正常的芯片在测试过程中失效,带来生产良品率下降。针对可测试设计的低功耗设计技术成为研究人员的关注焦点,希望能够提出新的设计方法和流程,它们能够对现有的主流设计方法不进行大的改动,实现最小代价地与当前的设计流程连接。本文首先介绍在处理器低功耗设计方面的基本概念和主要的研究内容,然后对其中的四个关键性问题进行研究,它们是,可复用的VLIW数字信号处理器原型、低功耗门控体系结构、有效的指令系统扩展、低功耗可测试性技术和设计方法学。为了验证从原型到低功耗设计的有效性,我们基于TSMC0.18微米工艺的技术对我们设计的低功耗DSP原型—Ares进行电路仿真,结果证实了用我们的方法,能够实现以较小的代价获得非常有效的功耗性能。针对当前日益标准化的视频编解码算法和通讯编码系统,我们对DSP的指令系统进行了有效地扩展,通过增加小代价的专用微体系结构有效提升DSP的运算效率。为了验证我们提出的基于分割的低功耗可测试性设计技术的有效性,我们在一款基于TSMC0.18微米的ARM9 SOC芯片的可测试性设计上应用了这一方法,实验结果证实了在测试过程中,我们获得了理想的测试覆盖率和较高的良品率。本文的贡献和创新性工作主要体现在以下几个方面:提出一种超长指令字DSP的虚拟原型,该原型具有一定的RISC结构特点,可看成是具有多个RISC微结构的并行处理器结构。该微结构试图将一个已有的VLIW指令系统映射为一个由多个可扩展的RISC结构组成的静态超标量结构,在此基础上,我们实现了命名为Ares的16位指令系统的VLIW结构。在Ares结构的基础上提出了一套减少无效时钟翻转的有效方法,把流水线的动态功耗降低到最小。提出了基于资源冲突监测的早期预测算法,对每一条独立通道的各级流水线结构进行了优化,同时给出了一个完整的Ares的时钟布局结构,实验数据显示了该算法能够在有限的附加电路的代价下实现非常显著的动态功耗优化。针对DSP的视频编解码和通讯编解码应用,提出了更高效的DSP指令扩展的方式以及高性能、低开销的微体系结构。提出了一种高性能、低开销的SAD微体系结构、一种高性能的AVS整数反变换结构和一种针对超长BCH码的高密度纠错结构。针对可测试性设计(DFT)的领域中遇到的功耗问题,提出了基于多时钟域的电路分割方法和EDA设计流程,并将其应用于大规模的生产测试实践中。在此基础上进一步提出了基于二部图的电路自动分割方法,该算法能够将分割电路带来的附加电路面积进一步降低,同时不牺牲电路的故障覆盖率和电路分割的“合理性”。更多还原

【Abstract】 The mobile computing and digital multimedia are becoming the trend of the ageof post-PC. It makes the digital circuits more and more rely on specific applications.Facing the requirement of a large quantity data and computation, application engineersfind that the various processor could not meet their design constrains. It is hard tomeet the time-to-market as well as the design schedule. To solve this problem, in thearea of low power design, people initiate a lot of research work on gated clock. Itsbasic idea is to minimize the dynamic power consumption by eliminating unnecessarytrigger of the circuit. Various techniques have been proposed in the past few years.Main efforts are focused on automatic insertion of gated logic block after the analysisof the net list. With the increment of the chip scale and the power consumption, morecomplex problems appear when in testing. That may lead to permanent damage to thecircuit under test due to high current density and overheating. Besides, the high rate ofcurrent in power and ground rail may cause excessive power/ground noise, which candisturb the normal operations of the circuit causing some good dies to fail the test andresulting in manufacturing loss. Low DFT methodology becomes the highlight of lowpower research. New design method and ?ow should be proposed. To be feasible andpractical, it should make least changes to the current design ?ow and should be at theminimum cost.Firstly, the basic idea and main research topics are introduced. Then we focuson the four key issues and propose the solutions. They are the prototype of VLIWDSP, the gated micro-architecture for low power consumption, the low power testingtechnology and design methodology. We implemented Ares—a low power prototypebased on the TSMC 0.18um Generic Process. The results of the simulation showedthe validity of our methodology. We gained significant power reduction at low costof extra circuit. With the standard video coding, communication and storage system,we extended the instruction set at very low cost. The micro-architectures presentedhere helped to increase the performance of the DSP significantly. In order to show thevalidity of the partition based DFT ?ow, we did the simulation on an ARM9-based SOCwhich was implemented by TSMC 0.18um Generic Process. Results shewed that in thetesting stage, we got good yield and high level fault coverage. The main contributions of the thesis can be summarized as follows:A virtual prototype of VLIW DSP is proposed, which features RISC architecture.This prototype can be seen as a parallel processor with multiple RISC micro-architectures. This VLIW architecture tries to map an existing VLIW instructionset into a static supper-scaler structure, that is composed of some extendableRISC micro-architecture. Based on this prototype, we implemented a 16-bit in-struction set VLIW structure named Ares.Based on Ares DSP core, we proposed a solution to minimize the dynamic powerconsumption of the pipeline, which focused on the elimination of useless trigger.A predictive algorithm is proposed based on the resource con?ict detection. Weoptimized the pipelines for every stand-alone channel of Ares and we presentedthe hierarchy of the total clock distribution of Ares. Simualtion results indicatedthat the algorithm brings significant dynamic power reduction at a considerablelow cost of the circuit.In the field of video coding and the error correction, several low cost architecturesare proposed to enhance the DSP instruction set. A low-cost high-performanceSAD architecture, a high-performance AVS inverse integer transform architec-ture and a high-density error-correcting architecture for ultra-long BCH Codesare presented.For the power consumption in the area of Design-for-Test, we proposed apartition-based method and EDA design ?ow by partitioning the chip into multi-ple independent clock domains. This ?ow is applied to the mass production andtesting. Moreover, in order to reduce the cost of the test circuit introduced by thepartition, to preserve the fault coverage, to produce more“reasonable”partition,an auto-partitioned algorithm is proposed.更多还原