【作者】 陈科明；

【导师】 姚庆栋； 刘鹏；

【作者基本信息】 浙江大学 ， 通信与信息系统， 2007， 博士

【摘要】 芯片设计技术和深亚微米工艺的进步使得系统集成在一块芯片中实现成为可能，嵌入式系统设计进入片上系统芯片时代。同时，多媒体技术快速发展，对系统提出更高的处理能力需求。多处理器系统芯片以其强大的处理能力、良好的灵活性等优点成为媒体处理解决方案的一个研究热点。本文作者参与了浙江大学信息与电子工程学系SoC R&D小组承担的具有自主知识产权的媒体系统芯片MediaSOC3221A和高性能多模式处理器RISC3202的研发工作。本文作为部分研究成果，着重探讨了媒体多处理器系统芯片中的数据搬运机制设计、多模式处理器核微结构设计以及音视频同步和系统任务调度等问题。媒体处理是一种高宽带流量的数据流处理，系统不仅需要有很强的数据运算能力，同时需要高效的数据搬运机制。DMA技术能有效地解决数据搬运问题，被广泛应用并有大量研究成果，但媒体多处理器系统芯片高复杂的内部结构对DMA数据搬运机制的设计和实现提出了新的挑战。本文分析了媒体数据的存储特点，阐述了面向媒体数据搬运的基于任务链表的二维DMA机制；针对基于片上总线的多处理系统芯片的特点，提出了集中式DMA控制器的设计方法；针对基于片上网络的媒体多处理器系统芯片的特点，提出了分散式DMA控制器的设计方法；分析了DMA控制器中的亚稳态问题，提出了异步电路的前端设计方法；最后实验表明，二维DMA机制能大大提高媒体系统芯片的性能。处理器是嵌入式媒体多处理器系统芯片的核心处理单元。目前嵌入式媒体应用范围比较广泛，不同的应用具有不同的特点，对处理器性能要求也不一样。本文在本课题组自主设计并通过验证的32位单发射处理器RISC3201的基础上，设计了满足多种应用特点的多模式处理器RISC3202。RISC3202可以在3种模式下运行：双发射模式、双核模式和双线程模式。在RISC3202的设计过程中，采用IP复用的设计策略，实现了多模式在微结构上的融合；分析了流水线中的结构竞争、数据竞争和控制竞争，并提出了相应的解决措施；提出了基于有限状态机的集中式流水线控制策略；实现了双线程模式下低开销的线程硬切换；实验数据表明，相对于RISC3201，RISC3202在流水线面积增加105％的同时，性能可提高70～80％。结合异构多处理器音视频解码系统芯片MediaSOC3221A的设计和实现，提出了基于反馈机制的全数字音视频同步的实现方案：利用系统的反馈信息实时地调整系统时钟频率和音频播放频率，实现系统时钟的精确恢复和音频的同步，利用调整视频帧的播放实现视频同步；为了减少多处理器媒体系统芯片总线任务调度过程中的处理器性能损失，从如何减少总线任务冲突的角度出发，提出了改变任务属性和调整任务优先级相结合的总线任务调度优化策略，实验结果表明，采用总线任务调度优化策略后，MediaSOC3221A在进行MPEG实时解码时处理器的性能损失从原来的4.7％减少到0.1％。更多还原

【Abstract】 Rapid improvement of chip design techniques and the deep-submicron technology havedriven the embedded system design into System-On-Chip (SoC) era. Meanwhile, more and morecomplex algorithms for media processing require higher performance of SoC. The programmablemulti-processor-based SoC is receiving more and more attention for its high performance andflexibility for real-time media processing.The author attended the development of a media SoC, namely MediaSoC3221A, and amulti-mode processor, namely RISC3202, which were both designed by the SoC R&D Group ofZhejiang University. The research work introduced in this thesis mainly concerns the design ofmedia multi-processor SoC (MP-SoC), including data transporting mechanism, multi-modeprocessor, audio/video synchronization and task scheduling.Media processing for large data streams requires not only high the data calculating ability, butalso the efficient data transporting mechanism. Direct memory access (DMA) technology totransport data is widely adopted into the designs. But more complex MP-SoC design brings thenew challenge to data transporting. The author analyzed the storage characteristics of media dataand described the task-chain based two-dimension DMA mechanism for media data transporting.The centralized DMA controller was designed for the bus-on-chip based MP-SoC. Meanwhile thedistributed DMA controller was designed for the network-on-chip based media MP-SoC. Amethod was proposed for the front design of asynchronous circuits. The experiments resultsindicated that the task-chain based two-dimension could effectively improve system performance.The processor is the key unit in embedded media MP-SoC. Based on 32 bit single-issueprocessor RISC3201, a multi-mode processor RISC3202 was designed to satisfy the requirementsof different applications. RISC3202 can operate with three modes: dual-issue mode, dual-coremode and dual-thread mode. During the design, the IP reuse methodology was adopted intomixing the micro-architecture of multiple modes. The pipeline hazards were analyzed and solvingmeasures proposed. A finite state machine (FSM) based centralized control scheme was proposedto supervise the pipeline activities. The thread switch with low cost was implemented. Comparingwith RISC3201, the performance of RISC3202 improved 70～80%, while the gate cost of pipelineincreased 105%.Base on the development of heterogeneous MP-SoC for audio/video decoding, a mechanismwith feed-back was implemented to synchronize audio and video. With system feed-back, thesystem clock frequency and the audio play-back frequency were adjusted in real time. Theplayback of video frame was adjusted according to synchronization. To reduce performance lossresulted from bus task conflicts in media processing, a scheme to optimize bus scheduling forMP-SoC was proposed. This scheme combined bus task property modification with bus taskpriority adjustment to optimize bus scheduling. Experiments showed that processor performanceloss in MediaSoC3221A was reduced from 4.7% to 0.1% during real-time MPEG decoding.更多还原