【作者】 段宝兴；

【导师】 张波；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2007， 博士

【摘要】 高压LDMOS（Lateral Double-diffused MOSFET）是高压集成电路HVIC（High Voltage Integrated Circuit）和功率集成电路PIC（Power Integrated Circuit）的关键技术。为了与低压电路在工艺上更好地兼容，设计具有薄外延层且能满足一定耐压的新型LDMOS是目前功率半导体技术的一个重要发展方向。SOI（Silicon-On-Insulator）集成技术由于具有隔离性能好、漏电流小、速度快、功耗低和抗辐照等优点，被誉为二十一世纪的集成技术，并被广泛应用于高性能HVIC和PIC中。高压器件中击穿电压与比导通电阻之间严重的矛盾关系，一直是众多学者研究的热点。对于应用于薄外延硅层和SOI基的LDMOS，纵向耐压低是这类器件应用的主要问题。将具有高耐压、低导通电阻的超结SJ（Super Junction）直接应用于LDMOS时具有的衬底辅助耗尽效应，限制了这类器件的发展。本论文主要思想是利用电场调制及电荷屏蔽效应，通过对影响横向高压器件特性的衬底改造，达到优化体内电场和表面电场的目的。本论文首次提出了一种不同于传统设计中通过优化器件表面电场以提高器件耐压的结终端技术，并称之为衬底终端技术，其核心是衬底的体电场调制效应。为了在超薄外延层上实现具有一定击穿电压的LDMOS，首次提出了REBULF（REduced BULk Field）技术。为了突破传统SOI LDMOS结构中因受自由面电荷为零高斯定理、纵向耐压受限，提出通过增加介质中电场的ENDIF技术。基于电场调制效应的衬底终端技术，本论文设计并研究了以下几种新型器件。（1）单面阶梯埋氧SOI（SBOSOI）。此结构利用了阶梯埋层的电场调制效应，而非传统设计中通过漂移区分区或线性掺杂技术优化表面电场。分析结果表明：漂移区较薄且Ⅰ层厚度为0.2～0.8μm时，SBOSOI结构较一般SOI结构可使比导通电阻降低40～50％，耐压提高30～50％：在Ⅰ层较薄、漂移区厚度小于1μm时，此结构可使耐压提高10～50％，比导通电阻降低10～50％。（2）双面阶梯埋氧SOI（D-SBOSOI）。此结构基于ENDIF技术而提出，具有增强电场调制效应、引入电荷层的电场屏蔽效应和形成的阶梯硅层有利于与低压部分隔离等优点。分析结果表明：表面电场在优化条件下近似达到理想的均匀分布；积累的空穴层屏蔽了局域埋氧层中高电场对SOI层的影响，Ⅰ层中的电场强度突破了一般结构中受自由面电荷为零高斯定理的限制关系，可高达200V／μm。（3）埋空隙部分SOI结构（APSOI）。此结构应用低介电系数埋层提高器件纵向耐压和优化表面电场。分析结果表明：空隙低的介电常数使器件在纵向突破了传统SiO₂埋层的耐压关系，在一定击穿电压下APSOI结构所需的埋层厚度为一般PSOI的1／4；当漂移区厚度为2μm，埋层厚度为1μm时可获得400V以上的耐压；漂移区厚度为2μm，埋层厚度为2μm时可获得600V以上的耐压。（4）具有P型埋层的部分SOI结构（BPSOI）。此结构应用P型埋层对N型漂移区电荷的充分补偿，使器件击穿电压提高的同时，比导通电阻减小。形成的P型低阻埋层也有利于缓解器件的自热效应。分析结果表明：表面电场出现新的峰而较一般PSOI结构更趋于均匀；增加的漂移区浓度使比导通电阻降低；新结构较一般PSOI结构在漂移区较薄（＜2μm）的情况下，击穿电压提高了52～58％，比导通电阻降低45～48％。（5）具有N⁺浮空层的REBULF LDMOS结构。此结构通过浮空的N⁺层将器件体内的电场重新分配，漏端电场降低而源端电场提高。REBULF技术的特点是继国际上提出降低器件表面电场RESURF（Reduce Surface Electric Field）技术之后，针对提高器件纵向耐压而提出，为提高器件耐压开辟了一条新路。分析结果表明：在优化的情况下，满足REBULF的条件为N⁺层的位置与衬底浓度的乘积不大于1×10¹²cm^-2；在保证低的比导通电阻条件下，REBULF LDMOS的击穿电压比一般RESURF LDMOS结构提高60％以上。（6）具有N⁺浮空层的SJ LDMOS。此结构是将REBULF技术与SJ技术相结合，即达到了降低体内高电场，提高纵向耐压的目的，而且也消除了衬底辅助耗尽效应。将SJ在横向器件中的应用进一步拓展到了高压区。（7）具有折叠硅表面的LDMOS结构。此结构通过刻蚀技术，将一般结构的硅表面刻蚀成矩型状，并用栅电极覆盖器件的漂移区表面。这种结构包括满足低耐压的FSOI-LDMOS和具有高耐压电荷积累层折叠硅表面FALDMOS结构。分析结果表明：在击穿电压小于40V的条件下，FSOI-LDMOS可以获得超低的比导通电阻；FALDMOS的击穿电压和比导通电阻关系打破了传统的硅极限。由于没有少数载流子的存储，折叠硅表面LDMOS结构的开关速度远较LIGBT的高。更多还原

【Abstract】 LDMOS （Lateral Double-diffused MOSFET） is a key device in HVIC （High Voltage Integrated Circuit） and PIC （Power Integrated Circuit）. In order to compatible with low-voltage circuit, novel LDMOS with thin epitaxy layer is a developing trend. SOI （Silicon-On-Insulator）, which is a mainstream of the 21st integrated technology, is applied to the new style HVIC and PIC owing to the improved isolation, reduced leakage current, high speed performance, low power dissipation and perfect irradiation hardness. It is a hotspot for many scholars to improve the trade-off between the breakdown voltage and specific on-resistance of LDMOS. The vertical breakdown voltage is low as applying thin epitaxy layer or SOI substrate in LDMOS. The application of SJ （ Super Junction） LDMOS is restricted due to the effect of substrate-assisted-depletion in the conventional SJ LDMOS when the super junction layer is adopted firsthand.The ideas of this paper are applying the effects of electric field modulation and charge shielding to optimize the surface and bulk electric field of LDMOS. A novel technology, which is called substrate terminal technology for the first time in this paper, is different from the conventional surface terminal technology in which the surface of device is processed. Its key is the modulation effect of the bulk electric field by rebuilding the substrate. In order to design an LDMOS with certain breakdown voltage in ultra-thin epitaxy layer, REBULF （REduced BULk Field） technology is put forward for the first time. ENDIF （ENhanced Dielectric layer Field） technology is proposed in this paper to break through the vertical breakdown voltage of SOI LDMOS due to the Gauss’ theorem without interface charge.By applying substrate terminal technology, several kinds of devices are designed as following:（1） SBOSOI （Step Buried Oxide SOI）: The surface electric field is optimized by applying the electric field modulation effect of step buried oxide, which is different from the case of the step or linear-drift-doping profiles. The results show that the breakdown voltage increases by 30-50% and the on-resistance decreases by 40-50% at the 0.2～0.8μm oxide thickness, and the breakdown voltage increases by 10～50% and the on-resistance decreases by 10～50% as the drift region thickness is less than 1μm.（2） D-SBOSOI （Double-Step Buried Oxide SOI）: Based on ENDIF technology the structure is provided with the merits of the developed electric field modulation, electric field shielding by introducing interface charge and simple isolation with low-voltage circuit by step buried oxide. The results show the surface electric field in this structure reaches nearly uniform distribution due to additive electric field modulation by double-step buried oxide, which results in the electric field of 200V/μm in the buried oxide layer.（3） APSOI （Air Partial SOI）: The surface electric field is optimised by applying the air gap with low permittivity. The results show only 1/4 thickness of buried layer is needed compared with normal PSOI structure at the same breakdown voltage. When the thickness of drift region and buried layer are both 2μm the breakdown voltage more than 600V can be obtained.（4） BPSOI （Buried Partial SOI）: The breakdown voltage is improved resulting from the additive electric field modulation by the P-type buried layer charges. The specific on-resistance is decreased as a result of increased doping of the drift region. The results show that the breakdown voltage is increased by 52～58% and the on-resistance is decreased by 45～48% compared with the conventional PSOI in virtue of 2-D MEDICI simulation.（5） N⁺ -Floating LDMOS: The mechanism of improved breakdown characteristics of this structure is the high electric field around the drain is reduced by N⁺-Floating layer which causes the redistribution of the bulk electric field in the drift region. REBULF, which provides a novel method to improve the vertical breakdown voltage of LDMOS, is proposed after the technology of RESURF （Reduce Surface Electric Field）. The critical condition of REBULF is the multiplication of the substrate’s doping and the distance between N⁺ -Floating layer and the drift region, which is less than l×10¹²cm^-2. The breakdown voltage of REBULF LDMOS is increased by 60% compared with RESURF LDMOS.（6） N⁺ -Floating SJ-LDMOS: The effect of substrate-assisted-depletion is suppressed by N⁺ -Floating Layer, which results from charge imbalance between the N-type and P-type pillars. The high electric field around the drain is reduced by N⁺ -Floating layer thanks to REBULF effect which causes the redistribution of the bulk electric field in the drift region, thus the substrate supports more voltage.（7） LDMOS with folded silicon: In this kind of technology the silicon substrate surface is trenched to form folded shape from the channel to the drain electrode and the gate is extended to the drain. Two structures of SOI-FALDMOS and FALDMOS are designed by applying this technology. It indicates that the ultra-low specific on-resistance is obtained with the breakdown voltage at less than 40 volts in SOI-FLDMOS. The ideal silicon limit of the breakdown voltage and specific on-resistance has been broken in FALDMOS. The turn-off of the FALDMOS is very fast due to no minority-carrier storage in the drift region compared with LIGBT.更多还原