【作者】 杨文荣；

【导师】 曹家麟；

【作者基本信息】 上海大学 ， 控制理论与控制工程， 2006， 博士

【摘要】 随着集成电路制造工艺和无线通信技术的迅速发展,实现全集成、多制式、低成本的无线收发器已成必然趋势。频率合成器作为无线收发器中的核心单元电路,是决定收发器性能好坏的关键因素,也是实现全集成无线收发器的主要难点。Σ-Δ小数频率合成器由于很好地解决了环路带宽与信道间距之间的矛盾,具有频率切换速度快、精度高、噪声小等优点,引起了人们越来越多的关注。本文简要回顾了无线通信系统中的频率合成技术,对高性能Σ-Δ小数频率合成器的设计方法进行了深入的研究。针对传统分频器存在的缺陷,设计实现了一种新型的CMOS高速多模可编程分频器,与传统分频器相比,该分频器具有结构简单、可重用性好等诸多优点。为了解决无源滤波器中电容占用面积太大、难以集成的难题,提出了一种电容倍乘方法,有效减小了电容的面积,实现了三阶无源滤波器的片上集成。本文对不同类型的Σ-Δ调制器的噪声成形效果进行了分析与比较,设计了一种输出为三位的三阶数字Σ-Δ调制器对小数分频比进行调制,改善了频率合成器的带内噪声和杂散性能,获得了比较满意的结果。本文在详细分析压控振荡器的相噪声特性的基础上,总结出集成平面螺旋电感和变容管的制作方法,提出了一些改进措施,改善了它们的Q值,并采用CMOS工艺,实现了一个差分型、低相噪声LC压控振荡器。另外,本文还讨论了频率合成器中其他重要单元电路的设计方法,如电荷泵、相频检测器、锁定检测电路等等。本文在上述方法的研究基础上,完成了2.4 GHz单片集成的Σ-Δ小数频率合成器的设计,并采用0.25μm CMOS工艺流片验证。测试结果表明,本文设计的频率合成器的技术指标均达到了设计要求,可适用于无绳电话、Home RF、WLAN、蓝牙、Zigbee等多种基于2.4 GHz无线通信标准的无线通信系统。本文的主要创新点如下:采用CMOS工艺,设计实现了一种新型的高速多模可编程分频器,克服了频率合成器的速度瓶颈;提出了一种电容倍乘方法,解决了无源滤波器中大电容难以集成的问题;针对多模可编程分频器的要求,实现了一个输入为20位、输出为3位的三阶数字Σ-Δ调制器。更多还原

【Abstract】 With the rapid development of IC (integrated circuits) fabrication processing and wireless communication technology, the implementation of a multi-standard, low-cost and fully integrated RF transceiver has become certainly the trend of development. The frequency synthesizer is a key building block in the RF transceiver. It is the determining factor of the overall performance of transceiver, and is also the biggest obstacle for its monolithic implementation. Due to theΣ-Δfractional-N frequency synthesizer completely overcomes the tradeoffs between loop bandwidth and channel spacing, and it can obtain a finer frequency resolution, lower phase noise and faster frequency switching, the more and more attentions have been put on it by the system designer recently.In this dissertation, the conventional techniques of frequency synthesis in wireless communication system are briefly reviewed, and the design methods of high performanceΣ-Δfractional-N frequency synthesizer are investigated. Several novel techniques are proposed to tackle the speed and integration bottlenecks of high-speed PLL.In order to overcome the disadvantage of traditional frequency divider, a new type of CMOS high-speed multi-modulus frequency divider is implemented, which is very suitable for the application of fractional-N frequency synthesizer. Comparing with the traditional frequency divider, it has the merits of high flexibility, high reusability and short design time. A capacitive scaler is proposed to reduce the chip area occupied by the large capacitors in the loop filter, thus an on-chip third-order passive filter is implemented. The key issue in the design of fractional-N frequency synthesizer is to eliminate the spurious tones come from fractional division. For this reason, the noise shaping effect of differentΣ-Δmodulators is analyzed, and a 3-bit third-orderΣ-Δmodulation technique as a spur reduction method to enhance the in-band noise and spur performance of synthesizer is proposed. Furthermore, the phase noise theory of LC VCO (voltage controlled oscillator) is thoroughly discussed, and the design techniques of spiral inductor and varactor are presented. Based on the analyzing and summarizing of the methods of improving their Q factor, a CMOS differential low phase noise LC-VCO is designed.更多还原