【作者】 陆思安；

【导师】 严晓浪；

【作者基本信息】 浙江大学 ， 电路与系统， 2003， 博士

【摘要】 随着集成电路制造技术的快速发展，系统芯片SOC逐渐成为现实。SOC将一个完整的系统集成在单个芯片上，从而缩小了系统的体积；SOC减少了SOB系统中芯片与芯片之间互连延时，从而提高了系统的性能；SOC采用基于核的设计方法，从而缩短了设计周期，降低了芯片成本。但SOC设计也遇到诸多挑战，测试复用就是其中的挑战之一。本文从测试复用的角度，系统地研究了可复用IP核以及系统芯片SOC的测试结构。 测试复用的第一个问题就是可复用IP核测试结构设计问题。常用核测试结构就是在IP核输入输出端口上添加测试环。本文在详细分析两种典型的测试环结构即IEEE P1500测试环和飞利浦的TestShell测试环的基础上提出了一种三态测试环结构。该结构允许共用同一条测试总线的IP核直接连接到测试总线上，从而保证测试数据可以在单个测试时钟周期内从核的测试激励源传送到IP核输入端口或从IP核输出端口传送到响应分析器。 测试环结构的关键是测试环单元设计。本文在详细分析两种典型测试环单元结构基础上，提出一种改进的测试环单元结构。它在传统的P1500测试环单元的基础上添加一个多路器，这不仅实现了对测试环单元的功能数据路径测试，而且解决了测试环扫描链在扫描移位过程中的安全移位问题，同时还可以大大降低扫描移位过程中产生的动态测试功耗。 测试复用的第二个问题就是SOC测试结构设计问题。SOC测试结构主要包括用于传送片上测试数据的测试访问机制TAM以及实现对片上核测试控制的芯片级测试控制器设计。当前应用最为广泛的是采用基于测试总线的TAM策略。本文详细分析了测试总线的原理，并给出基于测试总线的通用芯片测试结构。 在SOC中核的数目一般有十几个甚至几十个。为了实现对片上如此之多的IP核进行有序测试，需要进行测试调度。同时还需要设计一个芯片级测试控制器来控制整个芯片的测试。本文首次将测试调度问题与芯片级测试控制器设计问题结合起来，提出了一种能够灵活实现各种测试调度结果的芯片级测试控制器设计。 系统芯片SOC设计是一件非常复杂的事情。当前国内在芯片设计中IP核复用程度非常有限。本文针对这种情况提出了一种简单的芯片测试结构，该结构采用基于测试总线的TAM，并在模块设计过程中就考虑芯片测试问题，从而简化了芯片测试控制器的设计。 为了尽可能减少SOC总测试时间，降低测试费用，需要进行测试调度。测试调度是一个典型的NP问题。本文讨论了测试调度的线性规划模型，并给出了基于遗传算法的测试调度算法。更多还原

【Abstract】 With the fast development of IC manufacturing techniques, SOC(System on a Chip) is gradually becoming true. Firstly, SOC integrates a complete system on the single chip, so it reduces the volume of the system; Secondly, SOC greatly improves the performance of the system by reducing the delay between chips in SOB(System on Board); Third, SOC uses core-based design methodology which shortens the design period and lowers the cost of chips. However SOC design also meets many challenges, test reuse is one of them. This dissertation systematically discusses the test architectures of reusable IP cores and SOC.The first problem of test reuse is the design of test architecture of reusable IP cores. The general architecture is that a test wrapper is added to the I/O ports of the IP cores. A kind of wrapper, namely tri-state wrapper, is put forward based on analyzing two kinds of wrappers, to be specific IEEE P1500 wrapper and TestShell from Philip. The architecture lets the different cores directly connect to the same test bus, and test data can be transferred from source or sink to I/O ports of cores within a single test clock period.The key of wrapper architecture is the design of wrapper cell. An improved wrapper cell is presented based on analyzing two kinds of wrapper cells in the dissertation. It adds a mux to the traditional PI500 wrapper cell, which not only can test the data path of wrapper cells, but also can resolve the problem of safe shifting of scan chains during shifting as well as reduces the dynamic test power during scan shifting.The second problem of test reuse is the design of SOC test architecture. SOC test architecture chiefly includes the design of TAM(Test Access Mechanism) which is used to transfer test data on chip and the design of chip-level test controller which is used to control the test of the cores on chip. Test bus is used extensively in TAM design. The principle of test bus is analyzed and general chip test architecture based on test bus is presented in the dissertation.There are many cores in a SOC. In order to realize so many tests for these cores, test scheduling should be done and a chip-level test controller should also be designed. A kind of chip-level test controller which can flexibly carry out the result of test scheduling is presented, which also takes chip test scheduling into account.SOC design is very complicated. Reusing IP cores in chip design is so far little. A kind of simple test control architecture is put forward according to such a fact. The architecture uses test bus-based TAM, and takes the problem of chip test into account during module design to make the design of chip-level test controller simpler.For the sake of reducing total test time and lowering the test cost, test scheduling should be done. Test scheduling is a typical NP-complete problem. The linear programming model of test scheduling is discussed and an algorithm of test scheduling based on Genetic Algorithms is presented in the dissertation.更多还原