【作者】 陈勇；

【导师】 谢孟贤； 杨谟华；

【作者基本信息】 电子科技大学 ， 微电子学与固体电子学， 2001， 博士

【摘要】 本文基于小尺寸MOS器件热载流子退化的物理机理，对器件热载流子退化所导致的性能退化进行了深入的理论分析和相应的实验研究，给出了预测MOS器件和电路热载流子退化寿命的方法，并提出了抗热载流子退化的MOS模拟和数字电路结构。 首先，本文对超大规模集成电路中MOS器件尺寸缩小的限制及相应的可靠性问题进行了分析，特别是对小尺寸MOSFET的热载流子效应进行了较详细的讨论；并对国内外MOS器件和电路的热载流子可靠性研究进行了概述。 基于MOSFET偏压不能按比例缩小所导致的高电场，对MOSFET的热载流子产生机理进行了分析，导出了热载流子注入所引起的界面态的Si-H健断裂模型，并建立了表征器件热载流子效应的衬底电流模型。另外，比较讨论了P沟和N沟MOSFET的退化，对器件退化导致的电路延迟增加则引入了“时间因子”的概念来加以明确的表征；对器件退化的饱和效应和温度特性也作了分析概述。 针对MOS器件热载流子退化所引入的界面态，根据其沿沟道非均匀分布的模型，采用准二维分析方法对退化后器件的漏源电流、阈值电压和饱和区沟道电场作了详细的理论推导，并与实验结果和器件二维数值模拟软件MINIMOS 6.0的计算结果进行了验证比较。对器件的亚阈区导电和RF等特性的热载流子退化，也作了相应的分析。 为了分析研究高场热载流子效应对器件和电路特性可靠性的影响，采用自动测试与CAD技术相结合的监测系统，对国内沟道长度1.2μm、1.0μm和0.8μm的MOSFET进行了电应力退化实验，并根据实验结果提取了退化前后器件的BSIM2模型参数。 详细分析讨论了MOSFET的寿命与退化模型，并对电路中器件所受的动态应力与直流静态电应力进行了分析比较：根据实验结果改进了有效导电长度L_C模型；应用直流电应力实验数据进行了衬底电流模型中载流子速度饱和 电子科技大学博士论文临界电场E＊；、有效导电长度Lc以及退化参数H、m和 n的提取。概述了电路可靠性模拟软件BERTZ刀的CAS（CircuitAgingSAnulator）模块的基本原理：并以十一级环振为例，运用＊＊Rh刀进行了其中各个器件和总的电路寿命的预测。此外，还利用普通；挣山加速器进行了MOSFET的电子辐射实验，并提出了运用电子辐射实验预测器件寿命的方法。 最后，根据热载流子效应所导致的MOS器件性能参数的退化和其在模拟和数字运用环境下的特点，分别提出了抗热载流子退化的模拟和数字电路结构。即在受热载流子退化效应较严重的n－MOSFET漏极串联一肖特基二极管的新型CMOS数字电路结构和串联一工作于线性区的常开n－MOSFET的MOS模拟电路结构。经 SPICE及电路可靠性模拟软件 BERT 2．0对倒相器的模拟结果表明：新型CMOS数字电路结构结构使衬底电流降低约50％，器件的热载流子退化效应明显改善而不会增加电路延迟；巳该电路结构中肖特丛一级管可在NMOSFET漏极亘接制作肖特基金半接触来方便地实现，工艺简单又无须增加芯片而积。而串联常开n－MOSFET的模拟电路结构可使n－MOSFET输出电阻的退化大为减小同时还可改善器件小尺寸效应引起的输出电阻下降：采用该结构的＊＊OS运放与未采用的相比，其十年工作后增益的退化由23％下降为10％。可见新的电路结构大大降低了热载流于效应导致的电路寿命的下降，从而得到了MOS电路热载流子退化的解决方案。对抗热载流子退化的 MOS器件 LDDNghtly Doped Drain）结构及栅氧化层加固技术也作了简单的介绍。更多还原

【Abstract】 In this paper, based on the physical mechanisms of hot-carrier degradation of small dimensional MOSFET , the MOSFET characteristics degradation induced by the hot-carrier effect are deeply studied analytically and experimentally, The method to predict the lifetime of devices and circuits is given and MOS digital and analog circuit structures for the resistance of hot-carrier degradation are presented.First, the scaling limitation and relative reliability problems are analyzed for MOSFET in VLSI, especially for hot-carrier effects of small dimension MOSFET. And a review of the study of hot-carrier effects on devices and circuits is presented.Account for the high electrical field induced from the high applied voltage relative to small dimension device, the mechanism of hot-carrier generation is analysed, the Si-H bond broken model for hot-carrier injection and interface states generation is deduced and the substrate current model is developed. Also, the degradations of n-MOSFET and p-MOSFET are compared and the increase of delay-time induced by device degradation is represented by introducing "time-index", and the saturation effect and temperature characteristics of device degradation are described.Considering the unsymmetrical distribution of interface states induced by hot-carrier effects along the channel, the quasi-two-dimensional analysis methods are used to deduced the drain current, threshold voltage and electrical field in channel after hot-carrier degradation and the theoretical results are fully verified with the experimental data and M1NTMOS6.0 simulation output. The degradations of device output conductance, subthreshold conduction and RF characteristics are also analyzed.In order to investigate the effect of high-field hot-carrier on devices andcircuits, the electrical stress experiment is carried out with 1.2 n m, 1.0 n m and 0.8u m channel length home-made MOSFET’s by the monitor system with ATE andCAT technology. By using the fresh and degraded experiment data, BSIM2 modelparameters are extracted.The degradation and lifetime model is deeply discussed, dynamic and staticstress suffered by devices and circuits are compared and analyzed. A modified model for Lc is proposed for better fitting the experimental data and thesubstrate current model parameters Eerit and Lc , degradation parameter H, m,nare extracted by the static stress experiment results. Also, the principle of CAS module of the reliability simulator BERT 2.0 is given and a 11 stage ring oscillator is used as an example for BERT to predict the lifetime of devices and circuits. The electron radiation experiment for MOSFET’s is done with general linear accelerator and the simple method to predict the device lifetime by the electron radiation experiment is given.Finally, according to the MOSFET’s parameter degradation due to hot-carrier effects and different application environment of MOS devices on analog and digital circuits, the circuit structures for hot-carrier immunity are proposed for digital applications by adding a Schottky diode in series with the drain of the nMOSFET suffered heavily from hot-carrier degradation., and for analog applications by adding a normally-on nMOSFET in series with the n-MOSFET in an analog circuit respectively. According to SPICE3f5 and BERT2.0 simulation results, the substrate current of new structure CMOS inverter is suppressed to about 50% of its original value and good hot-carriers resistant behaviors are obtained without adding any extra delay. Also, by using the hot-carrier immiunity analog circuit structure, the output resistance degradation caused by the hot-carrier degradation is deeply supressed and the small-dimensional effect can be improved shown by the SPICE 3f5 simulation results, and the gain degradation of a CMOS operation amplifer after 10 years operation decreases from 23% to 10% with this structure according to BERT2.0 simulation. Therefore, the solution to the hot-carrier degradation of MOS circuits is obtained. The other hot-carrier immunity te更多还原