【作者】 韦健；

【导师】 姚庆栋；

【作者基本信息】 浙江大学 ， 通信与信息系统， 2001， 博士

【摘要】 随着集成电路进入深亚微米时代，功耗问题已成为超大规模集成电路设计考虑的重要因素。本文对逻辑电路层次低功耗设计、嵌入式RISC处理器设计及其低功耗研究进行了深入研究。 触发器是数字电路中的重要结构单元。在传统触发器结构的基础上，本文提出了单闩锁结构边沿触发器设计，它通过利用时钟信号的竞争冒险产生窄脉冲控制单一锁存器以实现触发器的一次状态转换功能。在二值单闩锁结构边沿触发器的基础上，把利用时钟信号竞争冒险的思想应用于三值电路中，提出了基于CMOS传输门的二值D型时钟信号竞争型边沿触发器。并且从传统主从结构触发器出发，提出了简化结构的维持阻塞型触发器设计。 针对数字电路中大量存在的冗余现象，本文讨论了冗余抑制原理以及相应的冗余抑制技术。为消除时钟信号的兀余跳变，提出了利用时钟两个方向跳变的双边沿触发器逻辑发计并应用于时序电路设计中。为抑制时序电路中的冗余现象，研究了时序电路的门控时钟技术，并利用T型触发器进行时序电路设计。利用冗余态的多码状态分配进行优先编码、通过对处于冗余态的触发器门控时钟来降低功耗。 超标量RISC微处理器是精简指令结构(RISC)的进一步发展，它通过增加并行流水执行单元并结合片上硬件动态调度来提高指令并行度。本文对超标量的体系结构特点进行了深入分折，探讨了超标量处理器中采用的各项技术。在此基础上，从系统芯片集成(SOC)的角度设计了嵌入式32bit定点超标量RISC软核，着重实现其中的跳转预测功能。并从系统层次对RISC处理器进行功耗分析，分别从改进指令体系结构、处理器数据通路、降低系统工作电压和动态降低功耗四个方面进行低功耗研究。更多还原

【Abstract】 With the coming of VLSFs Sub-micron era, Low-power technique has been a growing demand in VLSI design. This thesis is an investigation into the logic circuit low-power design, embedded RISC core design and its low-power research.Flip-flops are the basic units in digital circuit. Based on the construction of traditional flip-flop, we propose a novel edge-triggered flip-flip using one latch controlled by narrow pulse according to race-hazard of clock. Then this principle is adopted in ternary circuit, a new ternary D type edge-triggered flip-fiop based on CMOS transmission gate is proposed. From the concept of triditional master-slave flip-flop, we propose a simplified positive edge-triggered flip-flop and prove the traditional positive edge-triggered flip-flop is the master-slave flip-flop designed based on basic flip-flop with single-rail input.According to the redundancy in digital circuits, we investigate the diversified redundancy-restraining techniques for lower-power CMOS circuits. To erase the redundant transition of the clock, the logic design of double-edge-triggered flip-flop is presented and applied in sequential circuit design. To avoid the idleness state and the corresponding power dissipation in sequential circuits, a clock gating technique and a multi-code assignment using redundant state is adanced to reduce power dissipation.Superscalar RISC microprocessor is the further development of reduced instruction set computer, it improve the instruction-level-parallism by means of adding parallel pipelining function units and dynamic on-chip scheduling. This thesis anslysises the architecture and the diversified techniques of superscalar computer. A novel 32 bit embedded fix-point superscalar RISC core is developed. Then we analysis the power dissipation of RISC core from view of instruction-set-architecture, datapath, supply voltage and dynamic power optimization.更多还原