【作者】 杨伟建；

【导师】 姚庆栋；

【作者基本信息】 浙江大学 ， 通信与电子系统， 2001， 博士

【摘要】 高清晰度电视(High Definitlon Television--HDTV)是在模拟电视的基础上，为了达到高分辨率的图象质量性能而发展起来的，HDTV信源集成解码芯片是高清晰度电视接收机的一个关键部分。本文从芯片系统的整体入手，采用软硬件协同设计策略，重点从系统的软硬件分割?综合以及芯片系统的设计验证三个方面对该芯片系统的设计做了深入的研究。 信源集成解码芯片的设计，就是将系统层、视频和音频的解码算法映射到处理器设计空间的过程。本文提出了一种适合于该芯片设计的软硬件协同方法，通过分析TS流(TransportStream)数据包语法结构，以及开发系统层的解码算法，首先进行软硬件分割，然后着重针对芯片中的系统层解码过程提出一种新的软硬件综合方法。该综合方法的主要思想是：分析算法的特点，通过对算法程序归纳和建模，从模型中提取新指令，在降低算法复杂度的基础上，较大幅度地减少了程序存储器的容量，而为了支持新指令，只需要增加较少的硬件开销。 本文采用硬件描述语言-Verilog构建了一个含有RISC核的开发系统(虚拟机)，它作为信源解码芯片的软硬件协同仿真平台，为协同验证整个系统的各个功能模块提供了方便的工具，提高对系统的开发和调试效率。基于周期的指令集模型保证了软硬件的协同仿真和实现；可灵活扩充的指令集为处理器的升级和定制准备了坚实的基础；适当的硬件抽象化加速了系统的仿真速度；良好的界面为用户调试应用程序提供了类似于软件仿真器的环境。采用该仿真平台，同时验证了上述的面向应用软件的综合方法和RISC核硬件功能。 对于应用于信源集成解码芯片的系统软件—实时操作系统来说，存在着软件进程调度带来的开销与面向多媒体的芯片在进行数据交换时的实时性之间的矛盾。在本文中，采用软硬件协同设计的方法，提出了一种面向多媒体集成解码芯片应用的RTOS软硬件综合方法和基于协处理器的系统结构。通过将RTOS中的部分调度算法采用硬件实现，目的是在功能上解决大容量的数据传输引起的任务切换的实时性问题，同时减少片上RTOS软件部分的容量，有效缓解片上系统的存储瓶颈。更多还原

【Abstract】 HDTV (High Definition Television) is developed from analog television to achieve high resolving power of image quality. HDTV integrated source decoder is a key component of high definition television receiver. In this dissertation, using HW/SW (Hardware/Software) co design strategy, we develop the SOC (System On Chip) mainly focusing on the following three fields: system partition synthesis and verification.The design process of this SOC is to map decoding algorithms for TS (Transport Stream), video and audio into processor design space. In this dissertation, a new HW/SW co design technique is designed for HDTV SOC: After analyze the transport packet syntax architecture and decoding algorithm, system is first divided, then a new HW/SW synthesis technique is proposed: based on modeling of the algorithm, some new instructions are extracted to reduce the program size and complication, as a cost, only few hardware is added to support the new instruction set.In this dissertation, a RISC-based developing system (VM: Virtual Machine) is constructed in hardware description language-verilog. It works as a HW/SW simulation platform to co simulate function blocks if this SOC. Cycle-based instruction model guarantees the co simulation and implementation of hardware and software; Flexible-extended instruction set assures the processor upgrade; Adequate hardware abstraction accelerates the system’s simulation speed; Friendly user debugging interface provides the software-like simulating environment. The above synthesis technique and RISC core is co verified in this VM.RTOS (Real time operating system), which is designed as system software for this SOC, has a design problem that its overhead of software process scheduling conflicts with real-time requirement from data exchange in multimedia chip. In this dissertation, using HW/SW co design technique, a new RTOS HW/SW synthesis method and co-processor based system architecture is proposed. By divide part of RTOS software into hardware, above real-time problem is solved and software size is reduced to relax memory bottleneck in SOC.更多还原